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Searched refs:ANYEDGE (Results 1 – 15 of 15) sorted by relevance

/dports/cad/iverilog/verilog-11.0/
H A Dsync.cc46 if (pr->edge() == NetEvProbe::ANYEDGE) in is_synchronous()
H A Dnet_event.cc225 if (cur->edge() != NetEvProbe::ANYEDGE) { in nex_async_()
H A Dt-dll-proc.cc379 case NetEvProbe::ANYEDGE: in proc_assign_nb()
904 case NetEvProbe::ANYEDGE: in proc_wait()
H A Delaborate.cc4423 ev, NetEvProbe::ANYEDGE, in elaborate_st()
4492 if (expr_[idx]->type() != PEEvent::ANYEDGE) { in elaborate_st()
4548 unsigned pins = (expr_[idx]->type() == PEEvent::ANYEDGE) in elaborate_st()
4563 case PEEvent::ANYEDGE: in elaborate_st()
4565 NetEvProbe::ANYEDGE, pins); in elaborate_st()
4740 wait_event, NetEvProbe::ANYEDGE, in elaborate_wait()
5632 if (pr->edge() != NetEvProbe::ANYEDGE) in elaborate()
6561 if (prb->edge() == NetEvProbe::ANYEDGE) return; in check_event_probe_width()
6592 if (prb->edge() == NetEvProbe::ANYEDGE) { in check_ff_sensitivity()
H A DPExpr.h282 enum edge_t {ANYEDGE, POSEDGE, NEGEDGE, POSITIVE}; enumerator
H A Dexpr_synth.cc1380 ev, NetEvProbe::ANYEDGE, in make_func_trigger()
H A Dpform_dump.cc353 case PEEvent::ANYEDGE: in dump()
H A Ddesign_dump.cc1267 case ANYEDGE: in dump_node()
H A Dnetlist.cc2989 if (prb->edge() != NetEvProbe::ANYEDGE) return false; in do_expr_event_match()
H A Dparse.y3419 PEEvent*tmpe = new PEEvent(PEEvent::ANYEDGE, tmpi);
3470 { PEEvent*tmp = new PEEvent(PEEvent::ANYEDGE, $1);
H A Dt-dll.cc930 case NetEvProbe::ANYEDGE: in event()
H A Dnetlist.h3521 enum edge_t { ANYEDGE, POSEDGE, NEGEDGE }; enumerator
/dports/cad/iverilog/verilog-11.0/vhdlpp/
H A Ddebug.cc332 case ANYEDGE: in dump()
H A Dexpression_emit.cc612 case ANYEDGE: in emit()
H A Dexpression.h588 enum fun_t { NEGEDGE, ANYEDGE, POSEDGE }; enumerator