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Searched refs:AR5K_PHY_SLMT (Results 1 – 25 of 27) sorted by relevance

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/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/net/wireless/ath/ath5k/
H A Dinitvals.c926 { AR5K_PHY_SLMT, 0x00000080 },
1035 { AR5K_PHY_SLMT, 0x00000080 },
1172 { AR5K_PHY_SLMT, 0x00000080 },
H A Dreset.c313 ath5k_hw_reg_write(ah, 0x26, AR5K_PHY_SLMT); in ath5k_hw_set_sleep_clock()
320 ath5k_hw_reg_write(ah, 0x0a, AR5K_PHY_SLMT); in ath5k_hw_set_sleep_clock()
344 ath5k_hw_reg_write(ah, AR5K_PHY_SLMT_32MHZ, AR5K_PHY_SLMT); in ath5k_hw_set_sleep_clock()
H A Dreg.h2071 #define AR5K_PHY_SLMT 0x9874 macro
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/net/wireless/ath/ath5k/
H A Dinitvals.c926 { AR5K_PHY_SLMT, 0x00000080 },
1035 { AR5K_PHY_SLMT, 0x00000080 },
1172 { AR5K_PHY_SLMT, 0x00000080 },
H A Dreset.c313 ath5k_hw_reg_write(ah, 0x26, AR5K_PHY_SLMT); in ath5k_hw_set_sleep_clock()
320 ath5k_hw_reg_write(ah, 0x0a, AR5K_PHY_SLMT); in ath5k_hw_set_sleep_clock()
344 ath5k_hw_reg_write(ah, AR5K_PHY_SLMT_32MHZ, AR5K_PHY_SLMT); in ath5k_hw_set_sleep_clock()
H A Dreg.h2071 #define AR5K_PHY_SLMT 0x9874 macro
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/net/wireless/ath/ath5k/
H A Dinitvals.c926 { AR5K_PHY_SLMT, 0x00000080 },
1035 { AR5K_PHY_SLMT, 0x00000080 },
1172 { AR5K_PHY_SLMT, 0x00000080 },
H A Dreset.c313 ath5k_hw_reg_write(ah, 0x26, AR5K_PHY_SLMT); in ath5k_hw_set_sleep_clock()
320 ath5k_hw_reg_write(ah, 0x0a, AR5K_PHY_SLMT); in ath5k_hw_set_sleep_clock()
344 ath5k_hw_reg_write(ah, AR5K_PHY_SLMT_32MHZ, AR5K_PHY_SLMT); in ath5k_hw_set_sleep_clock()
H A Dreg.h2071 #define AR5K_PHY_SLMT 0x9874 macro
/dports/emulators/qemu60/qemu-6.0.0/roms/ipxe/src/drivers/net/ath/ath5k/
H A Dath5k_initvals.c928 { AR5K_PHY_SLMT, 0x00000080, AR5K_INI_WRITE },
1036 { AR5K_PHY_SLMT, 0x00000080, AR5K_INI_WRITE },
1174 { AR5K_PHY_SLMT, 0x00000080, AR5K_INI_WRITE },
H A Dreg.h2086 #define AR5K_PHY_SLMT 0x9874 macro
/dports/emulators/qemu42/qemu-4.2.1/roms/ipxe/src/drivers/net/ath/ath5k/
H A Dath5k_initvals.c928 { AR5K_PHY_SLMT, 0x00000080, AR5K_INI_WRITE },
1036 { AR5K_PHY_SLMT, 0x00000080, AR5K_INI_WRITE },
1174 { AR5K_PHY_SLMT, 0x00000080, AR5K_INI_WRITE },
H A Dreg.h2086 #define AR5K_PHY_SLMT 0x9874 macro
/dports/emulators/qemu-utils/qemu-4.2.1/roms/ipxe/src/drivers/net/ath/ath5k/
H A Dath5k_initvals.c928 { AR5K_PHY_SLMT, 0x00000080, AR5K_INI_WRITE },
1036 { AR5K_PHY_SLMT, 0x00000080, AR5K_INI_WRITE },
1174 { AR5K_PHY_SLMT, 0x00000080, AR5K_INI_WRITE },
H A Dreg.h2086 #define AR5K_PHY_SLMT 0x9874 macro
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/ipxe/src/drivers/net/ath/ath5k/
H A Dath5k_initvals.c928 { AR5K_PHY_SLMT, 0x00000080, AR5K_INI_WRITE },
1036 { AR5K_PHY_SLMT, 0x00000080, AR5K_INI_WRITE },
1174 { AR5K_PHY_SLMT, 0x00000080, AR5K_INI_WRITE },
H A Dreg.h2086 #define AR5K_PHY_SLMT 0x9874 macro
/dports/emulators/qemu5/qemu-5.2.0/roms/ipxe/src/drivers/net/ath/ath5k/
H A Dath5k_initvals.c928 { AR5K_PHY_SLMT, 0x00000080, AR5K_INI_WRITE },
1036 { AR5K_PHY_SLMT, 0x00000080, AR5K_INI_WRITE },
1174 { AR5K_PHY_SLMT, 0x00000080, AR5K_INI_WRITE },
H A Dreg.h2086 #define AR5K_PHY_SLMT 0x9874 macro
/dports/net/ipxe/ipxe-2265a65/src/drivers/net/ath/ath5k/
H A Dath5k_initvals.c928 { AR5K_PHY_SLMT, 0x00000080, AR5K_INI_WRITE },
1036 { AR5K_PHY_SLMT, 0x00000080, AR5K_INI_WRITE },
1174 { AR5K_PHY_SLMT, 0x00000080, AR5K_INI_WRITE },
H A Dreg.h2086 #define AR5K_PHY_SLMT 0x9874 macro
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/ipxe/src/drivers/net/ath/ath5k/
H A Dath5k_initvals.c928 { AR5K_PHY_SLMT, 0x00000080, AR5K_INI_WRITE },
1036 { AR5K_PHY_SLMT, 0x00000080, AR5K_INI_WRITE },
1174 { AR5K_PHY_SLMT, 0x00000080, AR5K_INI_WRITE },
/dports/emulators/qemu/qemu-6.2.0/roms/ipxe/src/drivers/net/ath/ath5k/
H A Dath5k_initvals.c928 { AR5K_PHY_SLMT, 0x00000080, AR5K_INI_WRITE },
1036 { AR5K_PHY_SLMT, 0x00000080, AR5K_INI_WRITE },
1174 { AR5K_PHY_SLMT, 0x00000080, AR5K_INI_WRITE },
/dports/sysutils/syslinux/syslinux-6.03/gpxe/src/drivers/net/ath5k/
H A Dath5k_initvals.c928 { AR5K_PHY_SLMT, 0x00000080, AR5K_INI_WRITE },
1036 { AR5K_PHY_SLMT, 0x00000080, AR5K_INI_WRITE },
1174 { AR5K_PHY_SLMT, 0x00000080, AR5K_INI_WRITE },
H A Dreg.h2086 #define AR5K_PHY_SLMT 0x9874 macro

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