/dports/security/py-pyvex/pyvex-9.0.5405/vex/priv/ |
H A D | guest_arm_helpers.c | 133 case ARMG_CC_OP_SUB: { in armg_calculate_flag_n() 213 case ARMG_CC_OP_SUB: { in armg_calculate_flag_z() 294 case ARMG_CC_OP_SUB: { in armg_calculate_flag_c() 375 case ARMG_CC_OP_SUB: { in armg_calculate_flag_v() 853 if (isU32(cond_n_op, (ARMCondEQ << 4) | ARMG_CC_OP_SUB)) { in guest_arm_spechelper() 858 if (isU32(cond_n_op, (ARMCondNE << 4) | ARMG_CC_OP_SUB)) { in guest_arm_spechelper() 864 if (isU32(cond_n_op, (ARMCondGT << 4) | ARMG_CC_OP_SUB)) { in guest_arm_spechelper() 870 if (isU32(cond_n_op, (ARMCondLE << 4) | ARMG_CC_OP_SUB)) { in guest_arm_spechelper() 876 if (isU32(cond_n_op, (ARMCondLT << 4) | ARMG_CC_OP_SUB)) { in guest_arm_spechelper() 1093 if (isU32(cc_op, ARMG_CC_OP_SUB)) { in guest_arm_spechelper() [all …]
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H A D | guest_arm_defs.h | 292 ARMG_CC_OP_SUB, /* DEP1 = argL (Rn), DEP2 = argR (shifter_op), enumerator
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H A D | guest_arm_toIR.c | 16479 setFlags_D1_D2( isCMN ? ARMG_CC_OP_ADD : ARMG_CC_OP_SUB, in disInstr_ARM_WRK() 19505 setFlags_D1_D2( isCMN ? ARMG_CC_OP_ADD : ARMG_CC_OP_SUB, in disInstr_THUMB_WRK() 19966 setFlags_D1_D2( ARMG_CC_OP_SUB, argL, argR, condT ); in disInstr_THUMB_WRK() 20232 setFlags_D1_D2( isSub ? ARMG_CC_OP_SUB : ARMG_CC_OP_ADD, in disInstr_THUMB_WRK() 20253 setFlags_D1_D2( isSub ? ARMG_CC_OP_SUB : ARMG_CC_OP_ADD, in disInstr_THUMB_WRK() 20393 setFlags_D1_D2( isSub ? ARMG_CC_OP_SUB : ARMG_CC_OP_ADD, in disInstr_THUMB_WRK() 20432 setFlags_D1_D2( ARMG_CC_OP_SUB, argL, argR, condT ); in disInstr_THUMB_WRK() 21019 setFlags_D1_D2( isCMN ? ARMG_CC_OP_ADD : ARMG_CC_OP_SUB, in disInstr_THUMB_WRK() 21085 setFlags_D1_D2( ARMG_CC_OP_SUB, argR, argL, condT ); in disInstr_THUMB_WRK() 21087 setFlags_D1_D2( ARMG_CC_OP_SUB, argL, argR, condT ); in disInstr_THUMB_WRK() [all …]
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/dports/devel/valgrind-lts/valgrind-dragonfly-dragonfly/VEX/priv/ |
H A D | guest_arm_helpers.c | 133 case ARMG_CC_OP_SUB: { in armg_calculate_flag_n() 213 case ARMG_CC_OP_SUB: { in armg_calculate_flag_z() 294 case ARMG_CC_OP_SUB: { in armg_calculate_flag_c() 375 case ARMG_CC_OP_SUB: { in armg_calculate_flag_v() 853 if (isU32(cond_n_op, (ARMCondEQ << 4) | ARMG_CC_OP_SUB)) { in guest_arm_spechelper() 858 if (isU32(cond_n_op, (ARMCondNE << 4) | ARMG_CC_OP_SUB)) { in guest_arm_spechelper() 864 if (isU32(cond_n_op, (ARMCondGT << 4) | ARMG_CC_OP_SUB)) { in guest_arm_spechelper() 870 if (isU32(cond_n_op, (ARMCondLE << 4) | ARMG_CC_OP_SUB)) { in guest_arm_spechelper() 876 if (isU32(cond_n_op, (ARMCondLT << 4) | ARMG_CC_OP_SUB)) { in guest_arm_spechelper() 1093 if (isU32(cc_op, ARMG_CC_OP_SUB)) { in guest_arm_spechelper() [all …]
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H A D | guest_arm_defs.h | 292 ARMG_CC_OP_SUB, /* DEP1 = argL (Rn), DEP2 = argR (shifter_op), enumerator
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H A D | guest_arm_toIR.c | 16410 setFlags_D1_D2( isCMN ? ARMG_CC_OP_ADD : ARMG_CC_OP_SUB, in disInstr_ARM_WRK() 19454 setFlags_D1_D2( isCMN ? ARMG_CC_OP_ADD : ARMG_CC_OP_SUB, in disInstr_THUMB_WRK() 19915 setFlags_D1_D2( ARMG_CC_OP_SUB, argL, argR, condT ); in disInstr_THUMB_WRK() 20175 setFlags_D1_D2( isSub ? ARMG_CC_OP_SUB : ARMG_CC_OP_ADD, in disInstr_THUMB_WRK() 20196 setFlags_D1_D2( isSub ? ARMG_CC_OP_SUB : ARMG_CC_OP_ADD, in disInstr_THUMB_WRK() 20336 setFlags_D1_D2( isSub ? ARMG_CC_OP_SUB : ARMG_CC_OP_ADD, in disInstr_THUMB_WRK() 20375 setFlags_D1_D2( ARMG_CC_OP_SUB, argL, argR, condT ); in disInstr_THUMB_WRK() 20962 setFlags_D1_D2( isCMN ? ARMG_CC_OP_ADD : ARMG_CC_OP_SUB, in disInstr_THUMB_WRK() 21028 setFlags_D1_D2( ARMG_CC_OP_SUB, argR, argL, condT ); in disInstr_THUMB_WRK() 21030 setFlags_D1_D2( ARMG_CC_OP_SUB, argL, argR, condT ); in disInstr_THUMB_WRK() [all …]
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/dports/devel/valgrind/valgrind-dragonfly-dragonfly/VEX/priv/ |
H A D | guest_arm_helpers.c | 133 case ARMG_CC_OP_SUB: { in armg_calculate_flag_n() 213 case ARMG_CC_OP_SUB: { in armg_calculate_flag_z() 294 case ARMG_CC_OP_SUB: { in armg_calculate_flag_c() 375 case ARMG_CC_OP_SUB: { in armg_calculate_flag_v() 853 if (isU32(cond_n_op, (ARMCondEQ << 4) | ARMG_CC_OP_SUB)) { in guest_arm_spechelper() 858 if (isU32(cond_n_op, (ARMCondNE << 4) | ARMG_CC_OP_SUB)) { in guest_arm_spechelper() 864 if (isU32(cond_n_op, (ARMCondGT << 4) | ARMG_CC_OP_SUB)) { in guest_arm_spechelper() 870 if (isU32(cond_n_op, (ARMCondLE << 4) | ARMG_CC_OP_SUB)) { in guest_arm_spechelper() 876 if (isU32(cond_n_op, (ARMCondLT << 4) | ARMG_CC_OP_SUB)) { in guest_arm_spechelper() 1093 if (isU32(cc_op, ARMG_CC_OP_SUB)) { in guest_arm_spechelper() [all …]
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H A D | guest_arm_defs.h | 292 ARMG_CC_OP_SUB, /* DEP1 = argL (Rn), DEP2 = argR (shifter_op), enumerator
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H A D | guest_arm_toIR.c | 16410 setFlags_D1_D2( isCMN ? ARMG_CC_OP_ADD : ARMG_CC_OP_SUB, in disInstr_ARM_WRK() 19454 setFlags_D1_D2( isCMN ? ARMG_CC_OP_ADD : ARMG_CC_OP_SUB, in disInstr_THUMB_WRK() 19915 setFlags_D1_D2( ARMG_CC_OP_SUB, argL, argR, condT ); in disInstr_THUMB_WRK() 20175 setFlags_D1_D2( isSub ? ARMG_CC_OP_SUB : ARMG_CC_OP_ADD, in disInstr_THUMB_WRK() 20196 setFlags_D1_D2( isSub ? ARMG_CC_OP_SUB : ARMG_CC_OP_ADD, in disInstr_THUMB_WRK() 20336 setFlags_D1_D2( isSub ? ARMG_CC_OP_SUB : ARMG_CC_OP_ADD, in disInstr_THUMB_WRK() 20375 setFlags_D1_D2( ARMG_CC_OP_SUB, argL, argR, condT ); in disInstr_THUMB_WRK() 20962 setFlags_D1_D2( isCMN ? ARMG_CC_OP_ADD : ARMG_CC_OP_SUB, in disInstr_THUMB_WRK() 21028 setFlags_D1_D2( ARMG_CC_OP_SUB, argR, argL, condT ); in disInstr_THUMB_WRK() 21030 setFlags_D1_D2( ARMG_CC_OP_SUB, argL, argR, condT ); in disInstr_THUMB_WRK() [all …]
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/dports/security/py-angr/angr-9.0.5405/angr/engines/vex/claripy/ |
H A D | ccall.py | 1400 ARMG_CC_OP_SUB = 2 # /* DEP1 = argL (Rn) = DEP2 = argR (shifter_op) = DEP3 = 0 */ variable 1425 elif concrete_op == ARMG_CC_OP_SUB: 1457 elif concrete_op == ARMG_CC_OP_SUB: 1487 elif concrete_op == ARMG_CC_OP_SUB: 1518 elif concrete_op == ARMG_CC_OP_SUB:
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