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Searched refs:ARM_SP (Results 1 – 25 of 105) sorted by relevance

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/dports/emulators/mgba/mgba-0.9.2/src/arm/
H A Disa-thumb.c275 DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD6, cpu->gprs[rd] = cpu->gprs[ARM_SP] + immediate)
347 DEFINE_INSTRUCTION_THUMB(ADD7, cpu->gprs[ARM_SP] += (opcode & 0x7F) << 2)
348 DEFINE_INSTRUCTION_THUMB(SUB4, cpu->gprs[ARM_SP] -= (opcode & 0x7F) << 2)
351 ARM_SP,
356 cpu->gprs[ARM_SP] = address)
359 ARM_SP,
364 cpu->gprs[ARM_SP] = address;
368 ARM_SP,
373 cpu->gprs[ARM_SP] = address)
376 ARM_SP,
[all …]
H A Ddecoder-thumb.c170 DEFINE_IMMEDIATE_WITH_REGISTER_MEM_THUMB(LDR4, LDR, ARM_SP, LOAD, 1)
171 DEFINE_IMMEDIATE_WITH_REGISTER_MEM_THUMB(STR3, STR, ARM_SP, STORE, 2)
174 DEFINE_IMMEDIATE_WITH_REGISTER_DATA_THUMB(ADD6, ADD, ARM_SP)
244 info->op1.reg = ARM_SP; \
253 DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POP, ARM_SP, LDM, ARM_MEMORY_INCREMENT_AFTER, LOAD, 0)
254 DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POPR, ARM_SP, LDM, ARM_MEMORY_INCREMENT_AFTER, LOAD, 1 << ARM_P…
255 DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSH, ARM_SP, STM, ARM_MEMORY_DECREMENT_BEFORE, STORE, 0)
256 DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSHR, ARM_SP, STM, ARM_MEMORY_DECREMENT_BEFORE, STORE, 1 << AR…
H A Darm.c36 cpu->bankedRegisters[oldBank][0] = cpu->gprs[ARM_SP]; in ARMSetPrivilegeMode()
38 cpu->gprs[ARM_SP] = cpu->bankedRegisters[newBank][0]; in ARMSetPrivilegeMode()
/dports/games/libretro-mgba/mgba-6186d45/src/arm/
H A Disa-thumb.c275 DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD6, cpu->gprs[rd] = cpu->gprs[ARM_SP] + immediate)
347 DEFINE_INSTRUCTION_THUMB(ADD7, cpu->gprs[ARM_SP] += (opcode & 0x7F) << 2)
348 DEFINE_INSTRUCTION_THUMB(SUB4, cpu->gprs[ARM_SP] -= (opcode & 0x7F) << 2)
351 ARM_SP,
356 cpu->gprs[ARM_SP] = address)
359 ARM_SP,
364 cpu->gprs[ARM_SP] = address;
368 ARM_SP,
373 cpu->gprs[ARM_SP] = address)
376 ARM_SP,
[all …]
H A Ddecoder-thumb.c168 DEFINE_IMMEDIATE_WITH_REGISTER_MEM_THUMB(LDR4, LDR, ARM_SP, LOAD_CYCLES, 1)
169 DEFINE_IMMEDIATE_WITH_REGISTER_MEM_THUMB(STR3, STR, ARM_SP, STORE_CYCLES, 2)
172 DEFINE_IMMEDIATE_WITH_REGISTER_DATA_THUMB(ADD6, ADD, ARM_SP)
240 info->op1.reg = ARM_SP; \
249 DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POP, ARM_SP, LDM, ARM_MEMORY_INCREMENT_AFTER, 0)
250 DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POPR, ARM_SP, LDM, ARM_MEMORY_INCREMENT_AFTER, 1 << ARM_PC)
251 DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSH, ARM_SP, STM, ARM_MEMORY_DECREMENT_BEFORE, 0)
252 DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSHR, ARM_SP, STM, ARM_MEMORY_DECREMENT_BEFORE, 1 << ARM_LR)
H A Darm.c38 cpu->bankedRegisters[oldBank][0] = cpu->gprs[ARM_SP]; in ARMSetPrivilegeMode()
40 cpu->gprs[ARM_SP] = cpu->bankedRegisters[newBank][0]; in ARMSetPrivilegeMode()
/dports/emulators/mgba/mgba-0.9.2/src/arm/debugger/
H A Ddebugger.c42 …if (frame && frame->frameBaseAddress < (uint32_t) cpu->gprs[ARM_SP] && currentStack == ARMSelectBa… in ARMDebuggerUpdateStackTraceInternal()
51 …} while (frame && frame->frameBaseAddress < (uint32_t) cpu->gprs[ARM_SP] && currentStack == ARMSel… in ARMDebuggerUpdateStackTraceInternal()
80 irqFrame = mStackTracePush(stack, pc, pc, cpu->gprs[ARM_SP], &cpu->regs); in ARMDebuggerUpdateStackTraceInternal()
137 } else if (frame && frame->frameBaseAddress == (uint32_t) cpu->gprs[ARM_SP]) { in ARMDebuggerUpdateStackTraceInternal()
158 …frame = mStackTracePush(stack, pc, destAddress + instructionLength, cpu->gprs[ARM_SP], &cpu->regs); in ARMDebuggerUpdateStackTraceInternal()
519 *value = cpu->gprs[ARM_SP]; in ARMDebuggerGetRegister()
555 cpu->gprs[ARM_SP] = value; in ARMDebuggerSetRegister()
/dports/emulators/gxemul/gxemul-0.6.3/src/machines/
H A Dmachine_test.cc171 cpu->cd.arm.r[ARM_SP] = machine->physical_ram_in_mb * 1048576 - 4096; in MACHINE_SETUP()
172 cpu->cd.arm.r[ARM_LR] = cpu->cd.arm.r[ARM_SP] + 32; in MACHINE_SETUP()
H A Dmachine_hpcarm.cc191 cpu->cd.arm.r[ARM_SP] = 0xc02dfff0; in MACHINE_SETUP()
/dports/devel/radare2/radare2-5.1.1/libr/asm/arch/include/
H A Dwine-arm.h44 #define ARM_SP ARM_R13 macro
/dports/multimedia/v4l-utils/linux-5.13-rc2/arch/arm/net/
H A Dbpf_jit_32.c1290 emit(ARM_MOV_R(ARM_IP, ARM_SP), ctx); in build_prologue()
1295 emit(ARM_MOV_R(ARM_FP, ARM_SP), ctx); in build_prologue()
1300 emit(ARM_SUB_I(bpf_r1[1], ARM_SP, SCRATCH_SIZE), ctx); in build_prologue()
1305 emit(ARM_SUB_I(ARM_SP, ARM_SP, ctx->stack_size), ctx); in build_prologue()
1326 u16 reg_set = CALLEE_POP_MASK | 1 << ARM_SP; in build_epilogue()
1327 emit(ARM_SUB_I(ARM_SP, ARM_FP, hweight16(reg_set) * 4), ctx); in build_epilogue()
1328 emit(ARM_LDM(ARM_SP, reg_set), ctx); in build_epilogue()
1331 emit(ARM_MOV_R(ARM_SP, ARM_FP), ctx); in build_epilogue()
1790 emit(ARM_ADD_I(ARM_SP, ARM_SP, imm8m(24)), ctx); // callee clean in build_insn()
/dports/multimedia/v4l_compat/linux-5.13-rc2/arch/arm/net/
H A Dbpf_jit_32.c1290 emit(ARM_MOV_R(ARM_IP, ARM_SP), ctx); in build_prologue()
1295 emit(ARM_MOV_R(ARM_FP, ARM_SP), ctx); in build_prologue()
1300 emit(ARM_SUB_I(bpf_r1[1], ARM_SP, SCRATCH_SIZE), ctx); in build_prologue()
1305 emit(ARM_SUB_I(ARM_SP, ARM_SP, ctx->stack_size), ctx); in build_prologue()
1326 u16 reg_set = CALLEE_POP_MASK | 1 << ARM_SP; in build_epilogue()
1327 emit(ARM_SUB_I(ARM_SP, ARM_FP, hweight16(reg_set) * 4), ctx); in build_epilogue()
1328 emit(ARM_LDM(ARM_SP, reg_set), ctx); in build_epilogue()
1331 emit(ARM_MOV_R(ARM_SP, ARM_FP), ctx); in build_epilogue()
1790 emit(ARM_ADD_I(ARM_SP, ARM_SP, imm8m(24)), ctx); // callee clean in build_insn()
/dports/multimedia/libv4l/linux-5.13-rc2/arch/arm/net/
H A Dbpf_jit_32.c1290 emit(ARM_MOV_R(ARM_IP, ARM_SP), ctx); in build_prologue()
1295 emit(ARM_MOV_R(ARM_FP, ARM_SP), ctx); in build_prologue()
1300 emit(ARM_SUB_I(bpf_r1[1], ARM_SP, SCRATCH_SIZE), ctx); in build_prologue()
1305 emit(ARM_SUB_I(ARM_SP, ARM_SP, ctx->stack_size), ctx); in build_prologue()
1326 u16 reg_set = CALLEE_POP_MASK | 1 << ARM_SP; in build_epilogue()
1327 emit(ARM_SUB_I(ARM_SP, ARM_FP, hweight16(reg_set) * 4), ctx); in build_epilogue()
1328 emit(ARM_LDM(ARM_SP, reg_set), ctx); in build_epilogue()
1331 emit(ARM_MOV_R(ARM_SP, ARM_FP), ctx); in build_epilogue()
1790 emit(ARM_ADD_I(ARM_SP, ARM_SP, imm8m(24)), ctx); // callee clean in build_insn()
/dports/devel/radare2/radare2-5.1.1/libr/asm/arch/arm/
H A Darmass64.c23 ARM_SP = 4, enumerator
235 if (op->operands[0].reg_type & ARM_SP || op->operands[1].reg_type & ARM_SP) { // alias of add in mov()
672 if (op->operands[1].reg_type != (ARM_REG64 | ARM_SP)) { in msr()
688 if (op->operands[0].reg_type != (ARM_REG64 | ARM_SP)) { in msr()
1142 op->operands[operand].reg_type |= ARM_SP; in parseOperands()
1169 op->operands[operand].reg_type = ARM_SP | ARM_REG64; in parseOperands()
/dports/emulators/mgba/mgba-0.9.2/include/mgba/internal/arm/
H A Darm.h16 ARM_SP = 13, enumerator
/dports/games/libretro-mgba/mgba-6186d45/include/mgba/internal/arm/
H A Darm.h16 ARM_SP = 13, enumerator
/dports/games/libretro-mgba/mgba-6186d45/src/arm/debugger/
H A Ddebugger.c336 *value = cpu->gprs[ARM_SP]; in ARMDebuggerGetRegister()
372 cpu->gprs[ARM_SP] = value; in ARMDebuggerSetRegister()
/dports/emulators/mgba/mgba-0.9.2/src/platform/qt/
H A DRegisterView.cpp122 …m_registers["sp"]->setText(QString("%1").arg((uint32_t) core->gprs[ARM_SP], 8, 16, QChar('0')).toU… in updateRegistersARM()
/dports/games/libretro-mgba/mgba-6186d45/src/platform/qt/
H A DRegisterView.cpp122 …m_registers["sp"]->setText(QString("%1").arg((uint32_t) core->gprs[ARM_SP], 8, 16, QChar('0')).toU… in updateRegistersARM()
/dports/emulators/gxemul/gxemul-0.6.3/src/include/
H A Dcpu_arm.h54 #define ARM_SP 13 macro
/dports/emulators/gxemul/gxemul-0.6.3/src/cpus/
H A Dcpu_arm.cc1513 addr = (cpu->cd.arm.r[ARM_SP] + (iw & 0xff) * 4) & ~3; in arm_cpu_interpret_thumb_SLOW()
1537 addr = (cpu->cd.arm.r[ARM_SP] + (iw & 0xff) * 4) & ~3; in arm_cpu_interpret_thumb_SLOW()
1551 cpu->cd.arm.r[ARM_SP] -= ((iw & 0x7f) << 2); in arm_cpu_interpret_thumb_SLOW()
1553 cpu->cd.arm.r[ARM_SP] += ((iw & 0x7f) << 2); in arm_cpu_interpret_thumb_SLOW()
1558 arm_push(cpu, &cpu->cd.arm.r[ARM_SP], 1, 0, 0, 1, (iw & 0xff) | in arm_cpu_interpret_thumb_SLOW()
1565 arm_pop(cpu, &cpu->cd.arm.r[ARM_SP], 0, 1, 0, 1, (iw & 0xff) | in arm_cpu_interpret_thumb_SLOW()
/dports/devel/capstone4/capstone-4.0.2/arch/ARM/
H A DARMGenRegisterInfo.inc29 ARM_SP = 12,
1191 …ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, ARM_PC,
1201 …M_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, ARM_APSR_…
1221 …ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR,
1241 ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, ARM_PC,
1261 ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR,
1311 ARM_SP,
/dports/devel/py-capstone/capstone-4.0.1/src/arch/ARM/
H A DARMGenRegisterInfo.inc29 ARM_SP = 12,
1191 …ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, ARM_PC,
1201 …M_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, ARM_APSR_…
1221 …ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR,
1241 ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, ARM_PC,
1261 ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR,
1311 ARM_SP,
/dports/devel/redasm/REDasm-2.1.1/LibREDasm/depends/capstone/arch/ARM/
H A DARMGenRegisterInfo.inc29 ARM_SP = 12,
1191 …ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, ARM_PC,
1201 …M_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, ARM_APSR_…
1221 …ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR,
1241 ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, ARM_PC,
1261 ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR,
1311 ARM_SP,
/dports/emulators/mgba/mgba-0.9.2/src/gba/
H A Dbios.c43 cpu->gprs[ARM_SP] = SP_BASE_IRQ; in _SoftReset()
47 cpu->gprs[ARM_SP] = SP_BASE_SUPERVISOR; in _SoftReset()
50 cpu->gprs[ARM_SP] = SP_BASE_SYSTEM; in _SoftReset()

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