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Searched refs:ARVALID (Results 1 – 12 of 12) sorted by relevance

/dports/cad/ghdl/ghdl-1.0.0/testsuite/gna/issue467/
H A Dtestbench2.vhdl25 signal ARVALID : std_logic; signal
64 ARVALID => ARVALID,
H A Daxi_master.vhd52 ARVALID : out std_logic; port
90 ARVALID <= '1';
147 ARVALID <= '0';
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/
H A Daxi4_pkg.vhd39 ARVALID : std_logic; record
85 ARVALID : std_logic; record
126 ARVALID => '0',
171 ARVALID : in std_logic; port in axi4_pkg.wb_axi4lite_bridge
216 l.ARVALID := f.ARVALID;
H A Dwb_axi4lite_bridge.vhd42 ARVALID : in std_logic; port
87 axi_in.ARVALID <= ARVALID;
H A Dxwb_axi4lite_bridge.vhd89 elsif (axi4_slave_i.ARVALID = '1') then
/dports/misc/tvm/incubator-tvm-0.6.1/vta/hardware/chisel/src/main/scala/shell/
H A DXilinxShell.scala75 m_axi_gmem.ARVALID := shell.io.mem.ar.valid
111 shell.io.host.ar.valid := s_axi_control.ARVALID
/dports/misc/py-tvm/incubator-tvm-0.6.1/vta/hardware/chisel/src/main/scala/shell/
H A DXilinxShell.scala75 m_axi_gmem.ARVALID := shell.io.mem.ar.valid
111 shell.io.host.ar.valid := s_axi_control.ARVALID
/dports/misc/tvm/incubator-tvm-0.6.1/vta/hardware/chisel/src/main/scala/interface/axi/
H A DAXI.scala257 val ARVALID = Input(Bool()) constant
292 val ARVALID = Output(Bool()) constant
/dports/misc/py-tvm/incubator-tvm-0.6.1/vta/hardware/chisel/src/main/scala/interface/axi/
H A DAXI.scala257 val ARVALID = Input(Bool()) constant
292 val ARVALID = Output(Bool()) constant
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/
H A Dn3xx_wr_top.vhd468 ARVALID => s00_axi_arvalid,
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/board/fasec/
H A Dxwrc_board_fasec.vhd600 ARVALID => s00_axi_arvalid,
/dports/cad/yosys/yosys-yosys-0.12/techlibs/xilinx/
H A Dcells_xtra.v27698 input ARVALID; port