AV1_MV_FP_SIZE (reference) in projects: dports

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Searched refs:AV1_MV_FP_SIZE (Results 1 – 10 of 10) sorted by relevance

/dports/lang/clover/mesa-21.3.6/src/gallium/drivers/radeon/
H A D	radeon_vcn_av1_default.h	295 #define AV1_MV_FP_SIZE 4 macro 300 uint16_t class0_fp_cdf[AV1_CLASS0_SIZE][CDF_SIZE(AV1_MV_FP_SIZE)]; 301 uint16_t fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 481 uint16_t nmvc_0_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 483 uint16_t nmvc_1_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 486 uint16_t ndvc_0_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 488 uint16_t ndvc_1_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 2748 uint16_t nmvc_0_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 2750 uint16_t nmvc_1_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 2753 uint16_t ndvc_0_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; [all …]
/dports/graphics/libosmesa/mesa-21.3.6/src/gallium/drivers/radeon/
H A D	radeon_vcn_av1_default.h	295 #define AV1_MV_FP_SIZE 4 macro 300 uint16_t class0_fp_cdf[AV1_CLASS0_SIZE][CDF_SIZE(AV1_MV_FP_SIZE)]; 301 uint16_t fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 481 uint16_t nmvc_0_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 483 uint16_t nmvc_1_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 486 uint16_t ndvc_0_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 488 uint16_t ndvc_1_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 2748 uint16_t nmvc_0_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 2750 uint16_t nmvc_1_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 2753 uint16_t ndvc_0_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; [all …]
/dports/graphics/libosmesa-gallium/mesa-21.3.6/src/gallium/drivers/radeon/
H A D	radeon_vcn_av1_default.h	295 #define AV1_MV_FP_SIZE 4 macro 300 uint16_t class0_fp_cdf[AV1_CLASS0_SIZE][CDF_SIZE(AV1_MV_FP_SIZE)]; 301 uint16_t fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 481 uint16_t nmvc_0_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 483 uint16_t nmvc_1_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 486 uint16_t ndvc_0_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 488 uint16_t ndvc_1_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 2748 uint16_t nmvc_0_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 2750 uint16_t nmvc_1_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 2753 uint16_t ndvc_0_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; [all …]
/dports/graphics/mesa-libs/mesa-21.3.6/src/gallium/drivers/radeon/
H A D	radeon_vcn_av1_default.h	295 #define AV1_MV_FP_SIZE 4 macro 300 uint16_t class0_fp_cdf[AV1_CLASS0_SIZE][CDF_SIZE(AV1_MV_FP_SIZE)]; 301 uint16_t fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 481 uint16_t nmvc_0_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 483 uint16_t nmvc_1_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 486 uint16_t ndvc_0_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 488 uint16_t ndvc_1_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 2748 uint16_t nmvc_0_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 2750 uint16_t nmvc_1_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 2753 uint16_t ndvc_0_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; [all …]
/dports/graphics/mesa-gallium-va/mesa-21.3.6/src/gallium/drivers/radeon/
H A D	radeon_vcn_av1_default.h	295 #define AV1_MV_FP_SIZE 4 macro 300 uint16_t class0_fp_cdf[AV1_CLASS0_SIZE][CDF_SIZE(AV1_MV_FP_SIZE)]; 301 uint16_t fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 481 uint16_t nmvc_0_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 483 uint16_t nmvc_1_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 486 uint16_t ndvc_0_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 488 uint16_t ndvc_1_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 2748 uint16_t nmvc_0_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 2750 uint16_t nmvc_1_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 2753 uint16_t ndvc_0_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; [all …]
/dports/graphics/mesa-gallium-vdpau/mesa-21.3.6/src/gallium/drivers/radeon/
H A D	radeon_vcn_av1_default.h	295 #define AV1_MV_FP_SIZE 4 macro 300 uint16_t class0_fp_cdf[AV1_CLASS0_SIZE][CDF_SIZE(AV1_MV_FP_SIZE)]; 301 uint16_t fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 481 uint16_t nmvc_0_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 483 uint16_t nmvc_1_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 486 uint16_t ndvc_0_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 488 uint16_t ndvc_1_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 2748 uint16_t nmvc_0_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 2750 uint16_t nmvc_1_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 2753 uint16_t ndvc_0_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; [all …]
/dports/graphics/mesa-dri-gallium/mesa-21.3.6/src/gallium/drivers/radeon/
H A D	radeon_vcn_av1_default.h	295 #define AV1_MV_FP_SIZE 4 macro 300 uint16_t class0_fp_cdf[AV1_CLASS0_SIZE][CDF_SIZE(AV1_MV_FP_SIZE)]; 301 uint16_t fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 481 uint16_t nmvc_0_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 483 uint16_t nmvc_1_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 486 uint16_t ndvc_0_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 488 uint16_t ndvc_1_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 2748 uint16_t nmvc_0_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 2750 uint16_t nmvc_1_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 2753 uint16_t ndvc_0_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; [all …]
/dports/graphics/mesa-gallium-xa/mesa-21.3.6/src/gallium/drivers/radeon/
H A D	radeon_vcn_av1_default.h	295 #define AV1_MV_FP_SIZE 4 macro 300 uint16_t class0_fp_cdf[AV1_CLASS0_SIZE][CDF_SIZE(AV1_MV_FP_SIZE)]; 301 uint16_t fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 481 uint16_t nmvc_0_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 483 uint16_t nmvc_1_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 486 uint16_t ndvc_0_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 488 uint16_t ndvc_1_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 2748 uint16_t nmvc_0_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 2750 uint16_t nmvc_1_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 2753 uint16_t ndvc_0_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; [all …]
/dports/graphics/mesa-devel/mesa-22.0-branchpoint-2059-ge8a63cf61ec/src/gallium/drivers/radeon/
H A D	radeon_vcn_av1_default.h	295 #define AV1_MV_FP_SIZE 4 macro 300 uint16_t class0_fp_cdf[AV1_CLASS0_SIZE][CDF_SIZE(AV1_MV_FP_SIZE)]; 301 uint16_t fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 481 uint16_t nmvc_0_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 483 uint16_t nmvc_1_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 486 uint16_t ndvc_0_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 488 uint16_t ndvc_1_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 2748 uint16_t nmvc_0_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 2750 uint16_t nmvc_1_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 2753 uint16_t ndvc_0_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; [all …]
/dports/graphics/mesa-dri/mesa-21.3.6/src/gallium/drivers/radeon/
H A D	radeon_vcn_av1_default.h	295 #define AV1_MV_FP_SIZE 4 macro 300 uint16_t class0_fp_cdf[AV1_CLASS0_SIZE][CDF_SIZE(AV1_MV_FP_SIZE)]; 301 uint16_t fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 481 uint16_t nmvc_0_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 483 uint16_t nmvc_1_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 486 uint16_t ndvc_0_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 488 uint16_t ndvc_1_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 2748 uint16_t nmvc_0_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 2750 uint16_t nmvc_1_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; 2753 uint16_t ndvc_0_fp_cdf[CDF_SIZE(AV1_MV_FP_SIZE)]; [all …]