/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/arm/mach-sunxi/ |
H A D | clock_sun8i_a83t.c | 81 writel(AXI_DIV_2 << AXI0_DIV_SHIFT | in clock_set_pll1() 82 AXI_DIV_2 << AXI1_DIV_SHIFT | in clock_set_pll1() 99 writel(AXI_DIV_2 << AXI0_DIV_SHIFT | in clock_set_pll1() 100 AXI_DIV_2 << AXI1_DIV_SHIFT | in clock_set_pll1()
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/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/arm/mach-sunxi/ |
H A D | clock_sun8i_a83t.c | 81 writel(AXI_DIV_2 << AXI0_DIV_SHIFT | in clock_set_pll1() 82 AXI_DIV_2 << AXI1_DIV_SHIFT | in clock_set_pll1() 99 writel(AXI_DIV_2 << AXI0_DIV_SHIFT | in clock_set_pll1() 100 AXI_DIV_2 << AXI1_DIV_SHIFT | in clock_set_pll1()
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/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/mach-sunxi/ |
H A D | clock_sun8i_a83t.c | 82 writel(AXI_DIV_2 << AXI0_DIV_SHIFT | in clock_set_pll1() 83 AXI_DIV_2 << AXI1_DIV_SHIFT | in clock_set_pll1() 100 writel(AXI_DIV_2 << AXI0_DIV_SHIFT | in clock_set_pll1() 101 AXI_DIV_2 << AXI1_DIV_SHIFT | in clock_set_pll1()
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/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/mach-sunxi/ |
H A D | clock_sun8i_a83t.c | 82 writel(AXI_DIV_2 << AXI0_DIV_SHIFT | in clock_set_pll1() 83 AXI_DIV_2 << AXI1_DIV_SHIFT | in clock_set_pll1() 100 writel(AXI_DIV_2 << AXI0_DIV_SHIFT | in clock_set_pll1() 101 AXI_DIV_2 << AXI1_DIV_SHIFT | in clock_set_pll1()
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/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/mach-sunxi/ |
H A D | clock_sun8i_a83t.c | 82 writel(AXI_DIV_2 << AXI0_DIV_SHIFT | in clock_set_pll1() 83 AXI_DIV_2 << AXI1_DIV_SHIFT | in clock_set_pll1() 100 writel(AXI_DIV_2 << AXI0_DIV_SHIFT | in clock_set_pll1() 101 AXI_DIV_2 << AXI1_DIV_SHIFT | in clock_set_pll1()
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/dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/arm/mach-sunxi/ |
H A D | clock_sun8i_a83t.c | 82 writel(AXI_DIV_2 << AXI0_DIV_SHIFT | in clock_set_pll1() 83 AXI_DIV_2 << AXI1_DIV_SHIFT | in clock_set_pll1() 100 writel(AXI_DIV_2 << AXI0_DIV_SHIFT | in clock_set_pll1() 101 AXI_DIV_2 << AXI1_DIV_SHIFT | in clock_set_pll1()
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/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/arm/mach-sunxi/ |
H A D | clock_sun8i_a83t.c | 82 writel(AXI_DIV_2 << AXI0_DIV_SHIFT | in clock_set_pll1() 83 AXI_DIV_2 << AXI1_DIV_SHIFT | in clock_set_pll1() 100 writel(AXI_DIV_2 << AXI0_DIV_SHIFT | in clock_set_pll1() 101 AXI_DIV_2 << AXI1_DIV_SHIFT | in clock_set_pll1()
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/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/mach-sunxi/ |
H A D | clock_sun8i_a83t.c | 82 writel(AXI_DIV_2 << AXI0_DIV_SHIFT | in clock_set_pll1() 83 AXI_DIV_2 << AXI1_DIV_SHIFT | in clock_set_pll1() 100 writel(AXI_DIV_2 << AXI0_DIV_SHIFT | in clock_set_pll1() 101 AXI_DIV_2 << AXI1_DIV_SHIFT | in clock_set_pll1()
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/dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/arm/mach-sunxi/ |
H A D | clock_sun8i_a83t.c | 82 writel(AXI_DIV_2 << AXI0_DIV_SHIFT | in clock_set_pll1() 83 AXI_DIV_2 << AXI1_DIV_SHIFT | in clock_set_pll1() 100 writel(AXI_DIV_2 << AXI0_DIV_SHIFT | in clock_set_pll1() 101 AXI_DIV_2 << AXI1_DIV_SHIFT | in clock_set_pll1()
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/dports/sysutils/u-boot-bananapi/u-boot-2021.07/arch/arm/mach-sunxi/ |
H A D | clock_sun8i_a83t.c | 82 writel(AXI_DIV_2 << AXI0_DIV_SHIFT | in clock_set_pll1() 83 AXI_DIV_2 << AXI1_DIV_SHIFT | in clock_set_pll1() 100 writel(AXI_DIV_2 << AXI0_DIV_SHIFT | in clock_set_pll1() 101 AXI_DIV_2 << AXI1_DIV_SHIFT | in clock_set_pll1()
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/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/arm/mach-sunxi/ |
H A D | clock_sun8i_a83t.c | 82 writel(AXI_DIV_2 << AXI0_DIV_SHIFT | in clock_set_pll1() 83 AXI_DIV_2 << AXI1_DIV_SHIFT | in clock_set_pll1() 100 writel(AXI_DIV_2 << AXI0_DIV_SHIFT | in clock_set_pll1() 101 AXI_DIV_2 << AXI1_DIV_SHIFT | in clock_set_pll1()
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/dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/arm/mach-sunxi/ |
H A D | clock_sun8i_a83t.c | 82 writel(AXI_DIV_2 << AXI0_DIV_SHIFT | in clock_set_pll1() 83 AXI_DIV_2 << AXI1_DIV_SHIFT | in clock_set_pll1() 100 writel(AXI_DIV_2 << AXI0_DIV_SHIFT | in clock_set_pll1() 101 AXI_DIV_2 << AXI1_DIV_SHIFT | in clock_set_pll1()
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/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/arm/mach-sunxi/ |
H A D | clock_sun8i_a83t.c | 82 writel(AXI_DIV_2 << AXI0_DIV_SHIFT | in clock_set_pll1() 83 AXI_DIV_2 << AXI1_DIV_SHIFT | in clock_set_pll1() 100 writel(AXI_DIV_2 << AXI0_DIV_SHIFT | in clock_set_pll1() 101 AXI_DIV_2 << AXI1_DIV_SHIFT | in clock_set_pll1()
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/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/mach-sunxi/ |
H A D | clock_sun8i_a83t.c | 82 writel(AXI_DIV_2 << AXI0_DIV_SHIFT | in clock_set_pll1() 83 AXI_DIV_2 << AXI1_DIV_SHIFT | in clock_set_pll1() 100 writel(AXI_DIV_2 << AXI0_DIV_SHIFT | in clock_set_pll1() 101 AXI_DIV_2 << AXI1_DIV_SHIFT | in clock_set_pll1()
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/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/arm/mach-sunxi/ |
H A D | clock_sun8i_a83t.c | 82 writel(AXI_DIV_2 << AXI0_DIV_SHIFT | in clock_set_pll1() 83 AXI_DIV_2 << AXI1_DIV_SHIFT | in clock_set_pll1() 100 writel(AXI_DIV_2 << AXI0_DIV_SHIFT | in clock_set_pll1() 101 AXI_DIV_2 << AXI1_DIV_SHIFT | in clock_set_pll1()
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/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/arch/arm/mach-sunxi/ |
H A D | clock_sun8i_a83t.c | 82 writel(AXI_DIV_2 << AXI0_DIV_SHIFT | in clock_set_pll1() 83 AXI_DIV_2 << AXI1_DIV_SHIFT | in clock_set_pll1() 100 writel(AXI_DIV_2 << AXI0_DIV_SHIFT | in clock_set_pll1() 101 AXI_DIV_2 << AXI1_DIV_SHIFT | in clock_set_pll1()
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/dports/sysutils/u-boot-wandboard/u-boot-2021.07/arch/arm/mach-sunxi/ |
H A D | clock_sun8i_a83t.c | 82 writel(AXI_DIV_2 << AXI0_DIV_SHIFT | in clock_set_pll1() 83 AXI_DIV_2 << AXI1_DIV_SHIFT | in clock_set_pll1() 100 writel(AXI_DIV_2 << AXI0_DIV_SHIFT | in clock_set_pll1() 101 AXI_DIV_2 << AXI1_DIV_SHIFT | in clock_set_pll1()
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/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/arm/mach-sunxi/ |
H A D | clock_sun8i_a83t.c | 81 writel(AXI_DIV_2 << AXI0_DIV_SHIFT | in clock_set_pll1() 82 AXI_DIV_2 << AXI1_DIV_SHIFT | in clock_set_pll1() 99 writel(AXI_DIV_2 << AXI0_DIV_SHIFT | in clock_set_pll1() 100 AXI_DIV_2 << AXI1_DIV_SHIFT | in clock_set_pll1()
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/arm/mach-sunxi/ |
H A D | clock_sun8i_a83t.c | 81 writel(AXI_DIV_2 << AXI0_DIV_SHIFT | in clock_set_pll1() 82 AXI_DIV_2 << AXI1_DIV_SHIFT | in clock_set_pll1() 99 writel(AXI_DIV_2 << AXI0_DIV_SHIFT | in clock_set_pll1() 100 AXI_DIV_2 << AXI1_DIV_SHIFT | in clock_set_pll1()
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/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/arm/mach-sunxi/ |
H A D | clock_sun8i_a83t.c | 82 writel(AXI_DIV_2 << AXI0_DIV_SHIFT | in clock_set_pll1() 83 AXI_DIV_2 << AXI1_DIV_SHIFT | in clock_set_pll1() 100 writel(AXI_DIV_2 << AXI0_DIV_SHIFT | in clock_set_pll1() 101 AXI_DIV_2 << AXI1_DIV_SHIFT | in clock_set_pll1()
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/dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/arm/mach-sunxi/ |
H A D | clock_sun8i_a83t.c | 82 writel(AXI_DIV_2 << AXI0_DIV_SHIFT | in clock_set_pll1() 83 AXI_DIV_2 << AXI1_DIV_SHIFT | in clock_set_pll1() 100 writel(AXI_DIV_2 << AXI0_DIV_SHIFT | in clock_set_pll1() 101 AXI_DIV_2 << AXI1_DIV_SHIFT | in clock_set_pll1()
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/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/arm/mach-sunxi/ |
H A D | clock_sun8i_a83t.c | 82 writel(AXI_DIV_2 << AXI0_DIV_SHIFT | in clock_set_pll1() 83 AXI_DIV_2 << AXI1_DIV_SHIFT | in clock_set_pll1() 100 writel(AXI_DIV_2 << AXI0_DIV_SHIFT | in clock_set_pll1() 101 AXI_DIV_2 << AXI1_DIV_SHIFT | in clock_set_pll1()
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/dports/sysutils/u-boot-pandaboard/u-boot-2021.07/arch/arm/mach-sunxi/ |
H A D | clock_sun8i_a83t.c | 82 writel(AXI_DIV_2 << AXI0_DIV_SHIFT | in clock_set_pll1() 83 AXI_DIV_2 << AXI1_DIV_SHIFT | in clock_set_pll1() 100 writel(AXI_DIV_2 << AXI0_DIV_SHIFT | in clock_set_pll1() 101 AXI_DIV_2 << AXI1_DIV_SHIFT | in clock_set_pll1()
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/dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/arch/arm/mach-sunxi/ |
H A D | clock_sun8i_a83t.c | 82 writel(AXI_DIV_2 << AXI0_DIV_SHIFT | in clock_set_pll1() 83 AXI_DIV_2 << AXI1_DIV_SHIFT | in clock_set_pll1() 100 writel(AXI_DIV_2 << AXI0_DIV_SHIFT | in clock_set_pll1() 101 AXI_DIV_2 << AXI1_DIV_SHIFT | in clock_set_pll1()
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/dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/arch/arm/mach-sunxi/ |
H A D | clock_sun8i_a83t.c | 82 writel(AXI_DIV_2 << AXI0_DIV_SHIFT | in clock_set_pll1() 83 AXI_DIV_2 << AXI1_DIV_SHIFT | in clock_set_pll1() 100 writel(AXI_DIV_2 << AXI0_DIV_SHIFT | in clock_set_pll1() 101 AXI_DIV_2 << AXI1_DIV_SHIFT | in clock_set_pll1()
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