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Searched refs:AZX_PCIREG_CGCTL (Results 1 – 6 of 6) sorted by relevance

/dports/multimedia/v4l_compat/linux-5.13-rc2/sound/soc/intel/skylake/
H A Dskl.h29 #define AZX_PCIREG_CGCTL 0x48 macro
H A Dskl.c95 update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_MISCBDCGE_MASK, val); in skl_enable_miscbdcge()
112 update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_ADSPDCGE, val); in skl_clock_power_gating()
/dports/multimedia/libv4l/linux-5.13-rc2/sound/soc/intel/skylake/
H A Dskl.h29 #define AZX_PCIREG_CGCTL 0x48 macro
H A Dskl.c95 update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_MISCBDCGE_MASK, val); in skl_enable_miscbdcge()
112 update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_ADSPDCGE, val); in skl_clock_power_gating()
/dports/multimedia/v4l-utils/linux-5.13-rc2/sound/soc/intel/skylake/
H A Dskl.h29 #define AZX_PCIREG_CGCTL 0x48 macro
H A Dskl.c95 update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_MISCBDCGE_MASK, val); in skl_enable_miscbdcge()
112 update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_ADSPDCGE, val); in skl_clock_power_gating()