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Searched refs:Add1_HiNc (Results 1 – 25 of 28) sorted by relevance

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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp2655 auto Add1_HiNc = B.buildAdd(S32, RcpHi, MulHi1_Hi); in legalizeUDIV_UREM64Impl() local
2667 B.buildUAdde(S32, S1, Add1_HiNc, MulHi2_Hi, Add1_Lo.getReg(1)); in legalizeUDIV_UREM64Impl()
H A DAMDGPUISelLowering.cpp1831 SDValue Add1_HiNc = DAG.getNode(ISD::ADD, DL, HalfVT, Rcp_Hi, Mulhi1_Hi); in LowerUDIVREM64() local
1844 SDValue Add2_HiC = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add1_HiNc, in LowerUDIVREM64()
/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp2655 auto Add1_HiNc = B.buildAdd(S32, RcpHi, MulHi1_Hi); in legalizeUDIV_UREM64Impl() local
2667 B.buildUAdde(S32, S1, Add1_HiNc, MulHi2_Hi, Add1_Lo.getReg(1)); in legalizeUDIV_UREM64Impl()
H A DAMDGPUISelLowering.cpp1831 SDValue Add1_HiNc = DAG.getNode(ISD::ADD, DL, HalfVT, Rcp_Hi, Mulhi1_Hi); in LowerUDIVREM64() local
1844 SDValue Add2_HiC = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add1_HiNc, in LowerUDIVREM64()
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp2893 auto Add1_HiNc = B.buildAdd(S32, RcpHi, MulHi1_Hi); in legalizeUDIV_UREM64Impl() local
2905 B.buildUAdde(S32, S1, Add1_HiNc, MulHi2_Hi, Add1_Lo.getReg(1)); in legalizeUDIV_UREM64Impl()
H A DAMDGPUISelLowering.cpp1845 SDValue Add1_HiNc = DAG.getNode(ISD::ADD, DL, HalfVT, Rcp_Hi, Mulhi1_Hi); in LowerUDIVREM64() local
1858 SDValue Add2_HiC = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add1_HiNc, in LowerUDIVREM64()
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp2985 auto Add1_HiNc = B.buildAdd(S32, RcpHi, MulHi1_Hi); in legalizeUnsignedDIV_REM64Impl() local
2997 B.buildUAdde(S32, S1, Add1_HiNc, MulHi2_Hi, Add1_Lo.getReg(1)); in legalizeUnsignedDIV_REM64Impl()
H A DAMDGPUISelLowering.cpp1905 SDValue Add1_HiNc = DAG.getNode(ISD::ADD, DL, HalfVT, Rcp_Hi, Mulhi1_Hi); in LowerUDIVREM64() local
1918 SDValue Add2_HiC = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add1_HiNc, in LowerUDIVREM64()
/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp2985 auto Add1_HiNc = B.buildAdd(S32, RcpHi, MulHi1_Hi); in legalizeUnsignedDIV_REM64Impl() local
2997 B.buildUAdde(S32, S1, Add1_HiNc, MulHi2_Hi, Add1_Lo.getReg(1)); in legalizeUnsignedDIV_REM64Impl()
H A DAMDGPUISelLowering.cpp1905 SDValue Add1_HiNc = DAG.getNode(ISD::ADD, DL, HalfVT, Rcp_Hi, Mulhi1_Hi); in LowerUDIVREM64() local
1918 SDValue Add2_HiC = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add1_HiNc, in LowerUDIVREM64()
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp2888 auto Add1_HiNc = B.buildAdd(S32, RcpHi, MulHi1_Hi); in legalizeUDIV_UREM64Impl() local
2900 B.buildUAdde(S32, S1, Add1_HiNc, MulHi2_Hi, Add1_Lo.getReg(1)); in legalizeUDIV_UREM64Impl()
H A DAMDGPUISelLowering.cpp1848 SDValue Add1_HiNc = DAG.getNode(ISD::ADD, DL, HalfVT, Rcp_Hi, Mulhi1_Hi); in LowerUDIVREM64() local
1861 SDValue Add2_HiC = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add1_HiNc, in LowerUDIVREM64()
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp2985 auto Add1_HiNc = B.buildAdd(S32, RcpHi, MulHi1_Hi); in legalizeUnsignedDIV_REM64Impl() local
2997 B.buildUAdde(S32, S1, Add1_HiNc, MulHi2_Hi, Add1_Lo.getReg(1)); in legalizeUnsignedDIV_REM64Impl()
H A DAMDGPUISelLowering.cpp1905 SDValue Add1_HiNc = DAG.getNode(ISD::ADD, DL, HalfVT, Rcp_Hi, Mulhi1_Hi); in LowerUDIVREM64() local
1918 SDValue Add2_HiC = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add1_HiNc, in LowerUDIVREM64()
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp3054 auto Add1_HiNc = B.buildAdd(S32, RcpHi, MulHi1_Hi); in legalizeUnsignedDIV_REM64Impl() local
3066 B.buildUAdde(S32, S1, Add1_HiNc, MulHi2_Hi, Add1_Lo.getReg(1)); in legalizeUnsignedDIV_REM64Impl()
H A DAMDGPUISelLowering.cpp1898 SDValue Add1_HiNc = DAG.getNode(ISD::ADD, DL, HalfVT, Rcp_Hi, Mulhi1_Hi); in LowerUDIVREM64() local
1911 SDValue Add2_HiC = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add1_HiNc, in LowerUDIVREM64()
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp2985 auto Add1_HiNc = B.buildAdd(S32, RcpHi, MulHi1_Hi); in legalizeUnsignedDIV_REM64Impl() local
2997 B.buildUAdde(S32, S1, Add1_HiNc, MulHi2_Hi, Add1_Lo.getReg(1)); in legalizeUnsignedDIV_REM64Impl()
H A DAMDGPUISelLowering.cpp1905 SDValue Add1_HiNc = DAG.getNode(ISD::ADD, DL, HalfVT, Rcp_Hi, Mulhi1_Hi); in LowerUDIVREM64() local
1918 SDValue Add2_HiC = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add1_HiNc, in LowerUDIVREM64()
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp2888 auto Add1_HiNc = B.buildAdd(S32, RcpHi, MulHi1_Hi); in legalizeUDIV_UREM64Impl() local
2900 B.buildUAdde(S32, S1, Add1_HiNc, MulHi2_Hi, Add1_Lo.getReg(1)); in legalizeUDIV_UREM64Impl()
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp2985 auto Add1_HiNc = B.buildAdd(S32, RcpHi, MulHi1_Hi); in legalizeUnsignedDIV_REM64Impl() local
2997 B.buildUAdde(S32, S1, Add1_HiNc, MulHi2_Hi, Add1_Lo.getReg(1)); in legalizeUnsignedDIV_REM64Impl()
/dports/devel/llvm70/llvm-7.0.1.src/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp1630 SDValue Add1_HiNc = DAG.getNode(ISD::ADD, DL, HalfVT, Rcp_Hi, Mulhi1_Hi); in LowerUDIVREM64() local
1643 SDValue Add2_HiC = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add1_HiNc, in LowerUDIVREM64()
/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp1716 SDValue Add1_HiNc = DAG.getNode(ISD::ADD, DL, HalfVT, Rcp_Hi, Mulhi1_Hi); in LowerUDIVREM64() local
1729 SDValue Add2_HiC = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add1_HiNc, in LowerUDIVREM64()
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp1716 SDValue Add1_HiNc = DAG.getNode(ISD::ADD, DL, HalfVT, Rcp_Hi, Mulhi1_Hi); in LowerUDIVREM64() local
1729 SDValue Add2_HiC = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add1_HiNc, in LowerUDIVREM64()
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp1716 SDValue Add1_HiNc = DAG.getNode(ISD::ADD, DL, HalfVT, Rcp_Hi, Mulhi1_Hi); in LowerUDIVREM64() local
1729 SDValue Add2_HiC = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add1_HiNc, in LowerUDIVREM64()
/dports/devel/llvm80/llvm-8.0.1.src/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp1650 SDValue Add1_HiNc = DAG.getNode(ISD::ADD, DL, HalfVT, Rcp_Hi, Mulhi1_Hi); in LowerUDIVREM64() local
1663 SDValue Add2_HiC = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add1_HiNc, in LowerUDIVREM64()

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