| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/AMDGPU/ |
| H A D | SIOptimizeExecMaskingPreRA.cpp | 84 static bool isDefBetween(const LiveRange &LR, SlotIndex AndIdx, in isDefBetween() argument
86 LiveQueryResult AndLRQ = LR.Query(AndIdx); in isDefBetween()
94 SlotIndex AndIdx = LIS->getInstructionIndex(And); in isDefBetween() local
98 return isDefBetween(LIS->getInterval(Reg), AndIdx, SelIdx); in isDefBetween()
101 if (isDefBetween(LIS->getRegUnit(*UI), AndIdx, SelIdx)) in isDefBetween()
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/ |
| H A D | SIOptimizeExecMaskingPreRA.cpp | 83 static bool isDefBetween(const LiveRange &LR, SlotIndex AndIdx, in isDefBetween() argument
85 LiveQueryResult AndLRQ = LR.Query(AndIdx); in isDefBetween()
93 SlotIndex AndIdx = LIS->getInstructionIndex(And); in isDefBetween() local
97 return isDefBetween(LIS->getInterval(Reg), AndIdx, SelIdx); in isDefBetween()
100 if (isDefBetween(LIS->getRegUnit(*UI), AndIdx, SelIdx)) in isDefBetween()
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AMDGPU/ |
| H A D | SIOptimizeExecMaskingPreRA.cpp | 83 static bool isDefBetween(const LiveRange &LR, SlotIndex AndIdx, in isDefBetween() argument
85 LiveQueryResult AndLRQ = LR.Query(AndIdx); in isDefBetween()
93 SlotIndex AndIdx = LIS->getInstructionIndex(And); in isDefBetween() local
97 return isDefBetween(LIS->getInterval(Reg), AndIdx, SelIdx); in isDefBetween()
100 if (isDefBetween(LIS->getRegUnit(*UI), AndIdx, SelIdx)) in isDefBetween()
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/AMDGPU/ |
| H A D | SIOptimizeExecMaskingPreRA.cpp | 83 static bool isDefBetween(const LiveRange &LR, SlotIndex AndIdx, in isDefBetween() argument
85 LiveQueryResult AndLRQ = LR.Query(AndIdx); in isDefBetween()
93 SlotIndex AndIdx = LIS->getInstructionIndex(And); in isDefBetween() local
97 return isDefBetween(LIS->getInterval(Reg), AndIdx, SelIdx); in isDefBetween()
100 if (isDefBetween(LIS->getRegUnit(*UI), AndIdx, SelIdx)) in isDefBetween()
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIOptimizeExecMaskingPreRA.cpp | 83 static bool isDefBetween(const LiveRange &LR, SlotIndex AndIdx, in isDefBetween() argument
85 LiveQueryResult AndLRQ = LR.Query(AndIdx); in isDefBetween()
93 SlotIndex AndIdx = LIS->getInstructionIndex(And); in isDefBetween() local
97 return isDefBetween(LIS->getInterval(Reg), AndIdx, SelIdx); in isDefBetween()
100 if (isDefBetween(LIS->getRegUnit(*UI), AndIdx, SelIdx)) in isDefBetween()
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/AMDGPU/ |
| H A D | SIOptimizeExecMaskingPreRA.cpp | 83 static bool isDefBetween(const LiveRange &LR, SlotIndex AndIdx, in isDefBetween() argument
85 LiveQueryResult AndLRQ = LR.Query(AndIdx); in isDefBetween()
93 SlotIndex AndIdx = LIS->getInstructionIndex(And); in isDefBetween() local
97 return isDefBetween(LIS->getInterval(Reg), AndIdx, SelIdx); in isDefBetween()
100 if (isDefBetween(LIS->getRegUnit(*UI), AndIdx, SelIdx)) in isDefBetween()
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/ |
| H A D | SIOptimizeExecMaskingPreRA.cpp | 83 static bool isDefBetween(const LiveRange &LR, SlotIndex AndIdx, in isDefBetween() argument
85 LiveQueryResult AndLRQ = LR.Query(AndIdx); in isDefBetween()
93 SlotIndex AndIdx = LIS->getInstructionIndex(And); in isDefBetween() local
97 return isDefBetween(LIS->getInterval(Reg), AndIdx, SelIdx); in isDefBetween()
100 if (isDefBetween(LIS->getRegUnit(*UI), AndIdx, SelIdx)) in isDefBetween()
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/AMDGPU/ |
| H A D | SIOptimizeExecMaskingPreRA.cpp | 83 static bool isDefBetween(const LiveRange &LR, SlotIndex AndIdx, in isDefBetween() argument
85 LiveQueryResult AndLRQ = LR.Query(AndIdx); in isDefBetween()
93 SlotIndex AndIdx = LIS->getInstructionIndex(And); in isDefBetween() local
97 return isDefBetween(LIS->getInterval(Reg), AndIdx, SelIdx); in isDefBetween()
100 if (isDefBetween(LIS->getRegUnit(*UI), AndIdx, SelIdx)) in isDefBetween()
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/ |
| H A D | SIOptimizeExecMaskingPreRA.cpp | 83 static bool isDefBetween(const LiveRange &LR, SlotIndex AndIdx,
85 LiveQueryResult AndLRQ = LR.Query(AndIdx);
93 SlotIndex AndIdx = LIS->getInstructionIndex(And);
97 return isDefBetween(LIS->getInterval(Reg), AndIdx, SelIdx);
100 if (isDefBetween(LIS->getRegUnit(*UI), AndIdx, SelIdx))
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 2764 SDValue AndIdx = DAG.getNode(ISD::AND, DL, MVT::i64, {Idx, Const1}); in lowerEXTRACT_VECTOR_ELT() local
2765 SDValue Shift = DAG.getNode(ISD::XOR, DL, MVT::i64, {AndIdx, Const1}); in lowerEXTRACT_VECTOR_ELT()
2822 SDValue AndIdx = DAG.getNode(ISD::AND, DL, MVT::i64, {Idx, Const1}); in lowerINSERT_VECTOR_ELT() local
2823 SDValue Shift = DAG.getNode(ISD::XOR, DL, MVT::i64, {AndIdx, Const1}); in lowerINSERT_VECTOR_ELT()
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 2764 SDValue AndIdx = DAG.getNode(ISD::AND, DL, MVT::i64, {Idx, Const1}); in lowerEXTRACT_VECTOR_ELT() local
2765 SDValue Shift = DAG.getNode(ISD::XOR, DL, MVT::i64, {AndIdx, Const1}); in lowerEXTRACT_VECTOR_ELT()
2822 SDValue AndIdx = DAG.getNode(ISD::AND, DL, MVT::i64, {Idx, Const1}); in lowerINSERT_VECTOR_ELT() local
2823 SDValue Shift = DAG.getNode(ISD::XOR, DL, MVT::i64, {AndIdx, Const1}); in lowerINSERT_VECTOR_ELT()
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 2762 SDValue AndIdx = DAG.getNode(ISD::AND, DL, MVT::i64, {Idx, Const1}); in lowerEXTRACT_VECTOR_ELT() local
2763 SDValue Shift = DAG.getNode(ISD::XOR, DL, MVT::i64, {AndIdx, Const1}); in lowerEXTRACT_VECTOR_ELT()
2819 SDValue AndIdx = DAG.getNode(ISD::AND, DL, MVT::i64, {Idx, Const1}); in lowerINSERT_VECTOR_ELT() local
2820 SDValue Shift = DAG.getNode(ISD::XOR, DL, MVT::i64, {AndIdx, Const1}); in lowerINSERT_VECTOR_ELT()
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 2764 SDValue AndIdx = DAG.getNode(ISD::AND, DL, MVT::i64, {Idx, Const1}); in lowerEXTRACT_VECTOR_ELT() local
2765 SDValue Shift = DAG.getNode(ISD::XOR, DL, MVT::i64, {AndIdx, Const1}); in lowerEXTRACT_VECTOR_ELT()
2822 SDValue AndIdx = DAG.getNode(ISD::AND, DL, MVT::i64, {Idx, Const1}); in lowerINSERT_VECTOR_ELT() local
2823 SDValue Shift = DAG.getNode(ISD::XOR, DL, MVT::i64, {AndIdx, Const1}); in lowerINSERT_VECTOR_ELT()
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 2764 SDValue AndIdx = DAG.getNode(ISD::AND, DL, MVT::i64, {Idx, Const1}); in lowerEXTRACT_VECTOR_ELT() local
2765 SDValue Shift = DAG.getNode(ISD::XOR, DL, MVT::i64, {AndIdx, Const1}); in lowerEXTRACT_VECTOR_ELT()
2822 SDValue AndIdx = DAG.getNode(ISD::AND, DL, MVT::i64, {Idx, Const1}); in lowerINSERT_VECTOR_ELT() local
2823 SDValue Shift = DAG.getNode(ISD::XOR, DL, MVT::i64, {AndIdx, Const1}); in lowerINSERT_VECTOR_ELT()
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 2764 SDValue AndIdx = DAG.getNode(ISD::AND, DL, MVT::i64, {Idx, Const1}); in lowerEXTRACT_VECTOR_ELT() local
2765 SDValue Shift = DAG.getNode(ISD::XOR, DL, MVT::i64, {AndIdx, Const1}); in lowerEXTRACT_VECTOR_ELT()
2822 SDValue AndIdx = DAG.getNode(ISD::AND, DL, MVT::i64, {Idx, Const1}); in lowerINSERT_VECTOR_ELT() local
2823 SDValue Shift = DAG.getNode(ISD::XOR, DL, MVT::i64, {AndIdx, Const1}); in lowerINSERT_VECTOR_ELT()
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 2762 SDValue AndIdx = DAG.getNode(ISD::AND, DL, MVT::i64, {Idx, Const1}); in lowerEXTRACT_VECTOR_ELT() local
2763 SDValue Shift = DAG.getNode(ISD::XOR, DL, MVT::i64, {AndIdx, Const1}); in lowerEXTRACT_VECTOR_ELT()
2819 SDValue AndIdx = DAG.getNode(ISD::AND, DL, MVT::i64, {Idx, Const1}); in lowerINSERT_VECTOR_ELT() local
2820 SDValue Shift = DAG.getNode(ISD::XOR, DL, MVT::i64, {AndIdx, Const1}); in lowerINSERT_VECTOR_ELT()
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 2764 SDValue AndIdx = DAG.getNode(ISD::AND, DL, MVT::i64, {Idx, Const1}); in lowerEXTRACT_VECTOR_ELT() local
2765 SDValue Shift = DAG.getNode(ISD::XOR, DL, MVT::i64, {AndIdx, Const1}); in lowerEXTRACT_VECTOR_ELT()
2822 SDValue AndIdx = DAG.getNode(ISD::AND, DL, MVT::i64, {Idx, Const1}); in lowerINSERT_VECTOR_ELT() local
2823 SDValue Shift = DAG.getNode(ISD::XOR, DL, MVT::i64, {AndIdx, Const1}); in lowerINSERT_VECTOR_ELT()
|