1 ///////////////////////////////////////////////////////////////////////// 2 // $Id: cpuid.h 14149 2021-02-16 18:57:49Z sshwarts $ 3 ///////////////////////////////////////////////////////////////////////// 4 // 5 // Copyright (c) 2010-2020 Stanislav Shwartsman 6 // Written by Stanislav Shwartsman [sshwarts at sourceforge net] 7 // 8 // This library is free software; you can redistribute it and/or 9 // modify it under the terms of the GNU Lesser General Public 10 // License as published by the Free Software Foundation; either 11 // version 2 of the License, or (at your option) any later version. 12 // 13 // This library is distributed in the hope that it will be useful, 14 // but WITHOUT ANY WARRANTY; without even the implied warranty of 15 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 // Lesser General Public License for more details. 17 // 18 // You should have received a copy of the GNU Lesser General Public 19 // License along with this library; if not, write to the Free Software 20 // Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA 21 // 22 ///////////////////////////////////////////////////////////////////////// 23 24 #ifndef BX_CPU_MODEL_SPECIFIC 25 #define BX_CPU_MODEL_SPECIFIC 26 27 struct cpuid_function_t { 28 Bit32u eax; 29 Bit32u ebx; 30 Bit32u ecx; 31 Bit32u edx; 32 }; 33 34 class VMCS_Mapping; 35 36 class bx_cpuid_t { 37 public: 38 bx_cpuid_t(BX_CPU_C *_cpu); 39 #if BX_SUPPORT_VMX 40 bx_cpuid_t(BX_CPU_C *_cpu, Bit32u vmcs_revision); 41 bx_cpuid_t(BX_CPU_C *_cpu, Bit32u vmcs_revision, const char *filename); 42 #endif ~bx_cpuid_t()43 virtual ~bx_cpuid_t() {} 44 45 void init(); 46 47 // return CPU name 48 virtual const char *get_name(void) const = 0; 49 get_cpu_extensions(Bit32u * extensions)50 BX_CPP_INLINE void get_cpu_extensions(Bit32u *extensions) const { 51 for (unsigned n=0; n < BX_ISA_EXTENSIONS_ARRAY_SIZE; n++) 52 extensions[n] = ia_extensions_bitmask[n]; 53 } 54 is_cpu_extension_supported(unsigned extension)55 BX_CPP_INLINE bool is_cpu_extension_supported(unsigned extension) const { 56 assert(extension < BX_ISA_EXTENSION_LAST); 57 return ia_extensions_bitmask[extension / 32] & (1 << (extension % 32)); 58 } 59 60 #if BX_SUPPORT_VMX get_vmx_extensions_bitmask(void)61 virtual Bit32u get_vmx_extensions_bitmask(void) const { return 0; } 62 #endif 63 #if BX_SUPPORT_SVM get_svm_extensions_bitmask(void)64 virtual Bit32u get_svm_extensions_bitmask(void) const { return 0; } 65 #endif 66 67 virtual void get_cpuid_leaf(Bit32u function, Bit32u subfunction, cpuid_function_t *leaf) const = 0; 68 69 virtual void dump_cpuid(void) const = 0; 70 71 void dump_features() const; 72 73 #if BX_CPU_LEVEL >= 5 rdmsr(Bit32u index,Bit64u * msr)74 virtual int rdmsr(Bit32u index, Bit64u *msr) { return -1; } wrmsr(Bit32u index,Bit64u msr)75 virtual int wrmsr(Bit32u index, Bit64u msr) { return -1; } 76 #endif 77 78 #if BX_SUPPORT_VMX get_vmcs()79 VMCS_Mapping* get_vmcs() { return &vmcs_map; } 80 #endif 81 82 protected: 83 BX_CPU_C *cpu; 84 85 unsigned nprocessors; 86 unsigned ncores; 87 unsigned nthreads; 88 89 Bit32u ia_extensions_bitmask[BX_ISA_EXTENSIONS_ARRAY_SIZE]; 90 enable_cpu_extension(unsigned extension)91 BX_CPP_INLINE void enable_cpu_extension(unsigned extension) { 92 assert(extension < BX_ISA_EXTENSION_LAST); 93 ia_extensions_bitmask[extension / 32] |= (1 << (extension % 32)); 94 warning_messages(extension); 95 } 96 disable_cpu_extension(unsigned extension)97 BX_CPP_INLINE void disable_cpu_extension(unsigned extension) { 98 assert(extension < BX_ISA_EXTENSION_LAST); 99 ia_extensions_bitmask[extension / 32] &= ~(1 << (extension % 32)); 100 } 101 102 void get_leaf_0(unsigned max_leaf, const char *vendor_string, cpuid_function_t *leaf, unsigned limited_max_leaf = 0x02) const; 103 void get_ext_cpuid_brand_string_leaf(const char *brand_string, Bit32u function, cpuid_function_t *leaf) const; 104 void get_cpuid_hidden_level(cpuid_function_t *leaf, const char *magic_string) const; 105 106 #if BX_SUPPORT_APIC 107 void get_std_cpuid_extended_topology_leaf(Bit32u subfunction, cpuid_function_t *leaf) const; 108 #endif 109 110 #if BX_CPU_LEVEL >= 6 111 void get_std_cpuid_xsave_leaf(Bit32u subfunction, cpuid_function_t *leaf) const; 112 #endif 113 114 Bit32u get_std_cpuid_leaf_7_ebx(Bit32u extra = 0) const; 115 Bit32u get_std_cpuid_leaf_7_ecx(Bit32u extra = 0) const; 116 117 void get_ext_cpuid_leaf_8(cpuid_function_t *leaf) const; 118 get_leaf(cpuid_function_t * leaf,Bit32u eax,Bit32u ebx,Bit32u ecx,Bit32u edx)119 BX_CPP_INLINE void get_leaf(cpuid_function_t *leaf, Bit32u eax, Bit32u ebx, Bit32u ecx, Bit32u edx) 120 { 121 leaf->eax = eax; 122 leaf->ebx = ebx; 123 leaf->ecx = ecx; 124 leaf->edx = edx; 125 } 126 get_reserved_leaf(cpuid_function_t * leaf)127 BX_CPP_INLINE void get_reserved_leaf(cpuid_function_t *leaf) const 128 { 129 leaf->eax = 0; 130 leaf->ebx = 0; 131 leaf->ecx = 0; 132 leaf->edx = 0; 133 } 134 135 void dump_cpuid_leaf(unsigned function, unsigned subfunction = 0) const; 136 void dump_cpuid(unsigned max_std_leaf, unsigned max_ext_leaf) const; 137 138 void warning_messages(unsigned extension) const; 139 140 #if BX_SUPPORT_VMX 141 VMCS_Mapping vmcs_map; 142 #endif 143 }; 144 145 extern const char *get_cpu_feature_name(unsigned feature); 146 147 typedef bx_cpuid_t* (*bx_create_cpuid_method)(BX_CPU_C *cpu); 148 149 // cpuid VMX features 150 #define BX_VMX_TPR_SHADOW (1 << 0) /* TPR shadow */ 151 #define BX_VMX_VIRTUAL_NMI (1 << 1) /* Virtual NMI */ 152 #define BX_VMX_APIC_VIRTUALIZATION (1 << 2) /* APIC Access Virtualization */ 153 #define BX_VMX_WBINVD_VMEXIT (1 << 3) /* WBINVD VMEXIT */ 154 #define BX_VMX_PERF_GLOBAL_CTRL (1 << 4) /* Save/Restore MSR_PERF_GLOBAL_CTRL */ 155 #define BX_VMX_MONITOR_TRAP_FLAG (1 << 5) /* Monitor trap Flag (MTF) */ 156 #define BX_VMX_X2APIC_VIRTUALIZATION (1 << 6) /* Virtualize X2APIC */ 157 #define BX_VMX_EPT (1 << 7) /* Extended Page Tables (EPT) */ 158 #define BX_VMX_VPID (1 << 8) /* VPID */ 159 #define BX_VMX_UNRESTRICTED_GUEST (1 << 9) /* Unrestricted Guest */ 160 #define BX_VMX_PREEMPTION_TIMER (1 << 10) /* VMX preemption timer */ 161 #define BX_VMX_SAVE_DEBUGCTL_DISABLE (1 << 11) /* Disable Save/Restore of MSR_DEBUGCTL */ 162 #define BX_VMX_PAT (1 << 12) /* Save/Restore MSR_PAT */ 163 #define BX_VMX_EFER (1 << 13) /* Save/Restore MSR_EFER */ 164 #define BX_VMX_DESCRIPTOR_TABLE_EXIT (1 << 14) /* Descriptor Table VMEXIT */ 165 #define BX_VMX_PAUSE_LOOP_EXITING (1 << 15) /* Pause Loop Exiting */ 166 #define BX_VMX_EPTP_SWITCHING (1 << 16) /* EPTP switching (VM Function 0) */ 167 #define BX_VMX_EPT_ACCESS_DIRTY (1 << 17) /* Extended Page Tables (EPT) A/D Bits */ 168 #define BX_VMX_VINTR_DELIVERY (1 << 18) /* Virtual Interrupt Delivery */ 169 #define BX_VMX_POSTED_INSTERRUPTS (1 << 19) /* Posted Interrupts support - not implemented yet */ 170 #define BX_VMX_VMCS_SHADOWING (1 << 20) /* VMCS Shadowing */ 171 #define BX_VMX_EPT_EXCEPTION (1 << 21) /* EPT Violation (#VE) exception */ 172 #define BX_VMX_PML (1 << 22) /* Page Modification Logging */ 173 #define BX_VMX_SPP (1 << 23) /* Sub Page Protection */ 174 #define BX_VMX_TSC_SCALING (1 << 24) /* TSC Scaling */ 175 #define BX_VMX_SW_INTERRUPT_INJECTION_ILEN_0 (1 << 25) /* Allow software interrupt injection with instruction length 0 */ 176 177 // CPUID defines - STD features CPUID[0x00000001].EDX 178 // ---------------------------- 179 180 // [0:0] FPU on chip 181 // [1:1] VME: Virtual-8086 Mode enhancements 182 // [2:2] DE: Debug Extensions (I/O breakpoints) 183 // [3:3] PSE: Page Size Extensions 184 // [4:4] TSC: Time Stamp Counter 185 // [5:5] MSR: RDMSR and WRMSR support 186 // [6:6] PAE: Physical Address Extensions 187 // [7:7] MCE: Machine Check Exception 188 // [8:8] CXS: CMPXCHG8B instruction 189 // [9:9] APIC: APIC on Chip 190 // [10:10] Reserved 191 // [11:11] SYSENTER/SYSEXIT support 192 // [12:12] MTRR: Memory Type Range Reg 193 // [13:13] PGE/PTE Global Bit 194 // [14:14] MCA: Machine Check Architecture 195 // [15:15] CMOV: Cond Mov/Cmp Instructions 196 // [16:16] PAT: Page Attribute Table 197 // [17:17] PSE-36: Physical Address Extensions 198 // [18:18] PSN: Processor Serial Number 199 // [19:19] CLFLUSH: CLFLUSH Instruction support 200 // [20:20] Reserved 201 // [21:21] DS: Debug Store 202 // [22:22] ACPI: Thermal Monitor and Software Controlled Clock Facilities 203 // [23:23] MMX Technology 204 // [24:24] FXSR: FXSAVE/FXRSTOR (also indicates CR4.OSFXSR is available) 205 // [25:25] SSE: SSE Extensions 206 // [26:26] SSE2: SSE2 Extensions 207 // [27:27] Self Snoop 208 // [28:28] Hyper Threading Technology 209 // [29:29] TM: Thermal Monitor 210 // [30:30] Reserved 211 // [31:31] PBE: Pending Break Enable 212 213 #define BX_CPUID_STD_X87 (1 << 0) 214 #define BX_CPUID_STD_VME (1 << 1) 215 #define BX_CPUID_STD_DEBUG_EXTENSIONS (1 << 2) 216 #define BX_CPUID_STD_PSE (1 << 3) 217 #define BX_CPUID_STD_TSC (1 << 4) 218 #define BX_CPUID_STD_MSR (1 << 5) 219 #define BX_CPUID_STD_PAE (1 << 6) 220 #define BX_CPUID_STD_MCE (1 << 7) 221 #define BX_CPUID_STD_CMPXCHG8B (1 << 8) 222 #define BX_CPUID_STD_APIC (1 << 9) 223 #define BX_CPUID_STD_RESERVED10 (1 << 10) 224 #define BX_CPUID_STD_SYSENTER_SYSEXIT (1 << 11) 225 #define BX_CPUID_STD_MTRR (1 << 12) 226 #define BX_CPUID_STD_GLOBAL_PAGES (1 << 13) 227 #define BX_CPUID_STD_MCA (1 << 14) 228 #define BX_CPUID_STD_CMOV (1 << 15) 229 #define BX_CPUID_STD_PAT (1 << 16) 230 #define BX_CPUID_STD_PSE36 (1 << 17) 231 #define BX_CPUID_STD_PROCESSOR_SERIAL_NUMBER (1 << 18) 232 #define BX_CPUID_STD_CLFLUSH (1 << 19) 233 #define BX_CPUID_STD_RESERVED20 (1 << 20) 234 #define BX_CPUID_STD_DEBUG_STORE (1 << 21) 235 #define BX_CPUID_STD_ACPI (1 << 22) 236 #define BX_CPUID_STD_MMX (1 << 23) 237 #define BX_CPUID_STD_FXSAVE_FXRSTOR (1 << 24) 238 #define BX_CPUID_STD_SSE (1 << 25) 239 #define BX_CPUID_STD_SSE2 (1 << 26) 240 #define BX_CPUID_STD_SELF_SNOOP (1 << 27) 241 #define BX_CPUID_STD_HT (1 << 28) 242 #define BX_CPUID_STD_THERMAL_MONITOR (1 << 29) 243 #define BX_CPUID_STD_RESERVED30 (1 << 30) 244 #define BX_CPUID_STD_PBE (1 << 31) 245 246 // CPUID defines - EXT features CPUID[0x00000001].ECX 247 // ---------------------------- 248 249 // [0:0] SSE3: SSE3 Instructions 250 // [1:1] PCLMULQDQ Instruction support 251 // [2:2] DTES64: 64-bit DS area 252 // [3:3] MONITOR/MWAIT support 253 // [4:4] DS-CPL: CPL qualified debug store 254 // [5:5] VMX: Virtual Machine Technology 255 // [6:6] SMX: Secure Virtual Machine Technology 256 // [7:7] EST: Enhanced Intel SpeedStep Technology 257 // [8:8] TM2: Thermal Monitor 2 258 // [9:9] SSSE3: SSSE3 Instructions 259 // [10:10] CNXT-ID: L1 context ID 260 // [11:11] IA32_DEBUG_INTERFACE MSR for silicon debug support 261 // [12:12] FMA Instructions support 262 // [13:13] CMPXCHG16B: CMPXCHG16B instruction support 263 // [14:14] xTPR update control 264 // [15:15] PDCM - Perfon and Debug Capability MSR 265 // [16:16] reserved 266 // [17:17] PCID: Process Context Identifiers 267 // [18:18] DCA - Direct Cache Access 268 // [19:19] SSE4.1 Instructions 269 // [20:20] SSE4.2 Instructions 270 // [21:21] X2APIC 271 // [22:22] MOVBE instruction 272 // [23:23] POPCNT instruction 273 // [24:24] TSC Deadline 274 // [25:25] AES Instructions 275 // [26:26] XSAVE extensions support 276 // [27:27] OSXSAVE support 277 // [28:28] AVX extensions support 278 // [29:29] AVX F16C - Float16 conversion support 279 // [30:30] RDRAND instruction 280 // [31:31] reserved 281 282 #define BX_CPUID_EXT_SSE3 (1 << 0) 283 #define BX_CPUID_EXT_PCLMULQDQ (1 << 1) 284 #define BX_CPUID_EXT_DTES64 (1 << 2) 285 #define BX_CPUID_EXT_MONITOR_MWAIT (1 << 3) 286 #define BX_CPUID_EXT_DS_CPL (1 << 4) 287 #define BX_CPUID_EXT_VMX (1 << 5) 288 #define BX_CPUID_EXT_SMX (1 << 6) 289 #define BX_CPUID_EXT_EST (1 << 7) 290 #define BX_CPUID_EXT_THERMAL_MONITOR2 (1 << 8) 291 #define BX_CPUID_EXT_SSSE3 (1 << 9) 292 #define BX_CPUID_EXT_CNXT_ID (1 << 10) 293 #define BX_CPUID_EXT_DEBUG_INTERFACE (1 << 11) 294 #define BX_CPUID_EXT_FMA (1 << 12) 295 #define BX_CPUID_EXT_CMPXCHG16B (1 << 13) 296 #define BX_CPUID_EXT_xTPR (1 << 14) 297 #define BX_CPUID_EXT_PDCM (1 << 15) 298 #define BX_CPUID_EXT_RESERVED16 (1 << 16) 299 #define BX_CPUID_EXT_PCID (1 << 17) 300 #define BX_CPUID_EXT_DCA (1 << 18) 301 #define BX_CPUID_EXT_SSE4_1 (1 << 19) 302 #define BX_CPUID_EXT_SSE4_2 (1 << 20) 303 #define BX_CPUID_EXT_X2APIC (1 << 21) 304 #define BX_CPUID_EXT_MOVBE (1 << 22) 305 #define BX_CPUID_EXT_POPCNT (1 << 23) 306 #define BX_CPUID_EXT_TSC_DEADLINE (1 << 24) 307 #define BX_CPUID_EXT_AES (1 << 25) 308 #define BX_CPUID_EXT_XSAVE (1 << 26) 309 #define BX_CPUID_EXT_OSXSAVE (1 << 27) 310 #define BX_CPUID_EXT_AVX (1 << 28) 311 #define BX_CPUID_EXT_AVX_F16C (1 << 29) 312 #define BX_CPUID_EXT_RDRAND (1 << 30) 313 #define BX_CPUID_EXT_RESERVED31 (1 << 31) 314 315 // CPUID defines - EXT3 features CPUID[0x00000007].EBX 316 // ----------------------------- 317 318 // [0:0] FS/GS BASE access instructions 319 // [1:1] Support for IA32_TSC_ADJUST MSR 320 // [2:2] SGX: Intel Software Guard Extensions 321 // [3:3] BMI1: Advanced Bit Manipulation Extensions 322 // [4:4] HLE: Hardware Lock Elision 323 // [5:5] AVX2 324 // [6:6] FDP Deprecation 325 // [7:7] SMEP: Supervisor Mode Execution Protection 326 // [8:8] BMI2: Advanced Bit Manipulation Extensions 327 // [9:9] Support for Enhanced REP MOVSB/STOSB 328 // [10:10] Support for INVPCID instruction 329 // [11:11] RTM: Restricted Transactional Memory 330 // [12:12] Supports Platform Quality of Service Monitoring (PQM) capability 331 // [13:13] Deprecates FPU CS and FPU DS values 332 // [14:14] Intel Memory Protection Extensions 333 // [15:15] Supports Platform Quality of Service Enforcement (PQE) capability 334 // [16:16] AVX512F instructions support 335 // [17:17] AVX512DQ instructions support 336 // [18:18] RDSEED instruction support 337 // [19:19] ADCX/ADOX instructions support 338 // [20:20] SMAP: Supervisor Mode Access Prevention 339 // [21:21] AVX512IFMA52 instructions support 340 // [22:22] Reserved 341 // [23:23] CLFLUSHOPT instruction 342 // [24:24] CLWB instruction 343 // [25:25] Intel Processor Trace 344 // [26:26] AVX512PF instructions support 345 // [27:27] AVX512ER instructions support 346 // [28:28] AVX512CD instructions support 347 // [29:29] SHA instructions support 348 // [30:30] AVX512BW instructions support 349 // [31:31] AVX512VL variable vector length support 350 351 #define BX_CPUID_EXT3_FSGSBASE (1 << 0) 352 #define BX_CPUID_EXT3_TSC_ADJUST (1 << 1) 353 #define BX_CPUID_EXT3_SGX (1 << 2) 354 #define BX_CPUID_EXT3_BMI1 (1 << 3) 355 #define BX_CPUID_EXT3_HLE (1 << 4) 356 #define BX_CPUID_EXT3_AVX2 (1 << 5) 357 #define BX_CPUID_EXT3_FDP_DEPRECATION (1 << 6) 358 #define BX_CPUID_EXT3_SMEP (1 << 7) 359 #define BX_CPUID_EXT3_BMI2 (1 << 8) 360 #define BX_CPUID_EXT3_ENCHANCED_REP_STRINGS (1 << 9) 361 #define BX_CPUID_EXT3_INVPCID (1 << 10) 362 #define BX_CPUID_EXT3_RTM (1 << 11) 363 #define BX_CPUID_EXT3_QOS_MONITORING (1 << 12) 364 #define BX_CPUID_EXT3_DEPRECATE_FCS_FDS (1 << 13) 365 #define BX_CPUID_EXT3_MPX (1 << 14) 366 #define BX_CPUID_EXT3_QOS_ENFORCEMENT (1 << 15) 367 #define BX_CPUID_EXT3_AVX512F (1 << 16) 368 #define BX_CPUID_EXT3_AVX512DQ (1 << 17) 369 #define BX_CPUID_EXT3_RDSEED (1 << 18) 370 #define BX_CPUID_EXT3_ADX (1 << 19) 371 #define BX_CPUID_EXT3_SMAP (1 << 20) 372 #define BX_CPUID_EXT3_AVX512IFMA52 (1 << 21) 373 #define BX_CPUID_EXT3_RESERVED22 (1 << 22) 374 #define BX_CPUID_EXT3_CLFLUSHOPT (1 << 23) 375 #define BX_CPUID_EXT3_CLWB (1 << 24) 376 #define BX_CPUID_EXT3_PROCESSOR_TRACE (1 << 25) 377 #define BX_CPUID_EXT3_AVX512PF (1 << 26) 378 #define BX_CPUID_EXT3_AVX512ER (1 << 27) 379 #define BX_CPUID_EXT3_AVX512CD (1 << 28) 380 #define BX_CPUID_EXT3_SHA (1 << 29) 381 #define BX_CPUID_EXT3_AVX512BW (1 << 30) 382 #define BX_CPUID_EXT3_AVX512VL (1 << 31) 383 384 // CPUID defines - EXT4 features CPUID[0x00000007].ECX 385 // ----------------------------- 386 387 // [0:0] PREFETCHWT1 instruction support 388 // [1:1] AVX512 VBMI instructions support 389 // [2:2] UMIP: Supports user-mode instruction prevention 390 // [3:3] PKU: Protection keys for user-mode pages. 391 // [4:4] OSPKE: OS has set CR4.PKE to enable protection keys 392 // [5:5] WAITPKG (TPAUSE/UMONITOR/UMWAIT) support 393 // [6:6] AVX512 VBMI2 instructions support 394 // [7:7] CET_SS: Support CET Shadow Stack 395 // [8:8] GFNI instructions support 396 // [9:9] VAES instructions support 397 // [10:10] VPCLMULQDQ instruction support 398 // [11:11] AVX512 VNNI instructions support 399 // [12:12] AVX512 BITALG instructions support 400 // [13:13] reserved 401 // [14:14] AVX512 VPOPCNTDQ: AVX512 VPOPCNTD/VPOPCNTQ instructions 402 // [15:15] reserved 403 // [16:16] LA57: LA57 and 5-level paging 404 // [21:17] reserved 405 // [22:22] RDPID: Read Processor ID support 406 // [23:23] Keylocker 407 // [24:23] reserved 408 // [25:25] CLDEMOTE: CLDEMOTE instruction support 409 // [26:26] reserved 410 // [27:27] MOVDIRI: MOVDIRI instruction support 411 // [28:28] MOVDIR64B: MOVDIR64B instruction support 412 // [29:29] ENQCMD: Enqueue Stores support 413 // [30:30] SGX_LC: SGX Launch Configuration 414 // [31:31] PKS: Protection keys for supervisor-mode pages 415 416 #define BX_CPUID_EXT4_PREFETCHWT1 (1 << 0) 417 #define BX_CPUID_EXT4_AVX512_VBMI (1 << 1) 418 #define BX_CPUID_EXT4_UMIP (1 << 2) 419 #define BX_CPUID_EXT4_PKU (1 << 3) 420 #define BX_CPUID_EXT4_OSPKE (1 << 4) 421 #define BX_CPUID_EXT4_WAITPKG (1 << 5) 422 #define BX_CPUID_EXT4_AVX512_VBMI2 (1 << 6) 423 #define BX_CPUID_EXT4_CET_SS (1 << 7) 424 #define BX_CPUID_EXT4_GFNI (1 << 8) 425 #define BX_CPUID_EXT4_VAES (1 << 9) 426 #define BX_CPUID_EXT4_VPCLMULQDQ (1 << 10) 427 #define BX_CPUID_EXT4_AVX512_VNNI (1 << 11) 428 #define BX_CPUID_EXT4_AVX512_BITALG (1 << 12) 429 #define BX_CPUID_EXT4_RESERVED13 (1 << 13) 430 #define BX_CPUID_EXT4_AVX512_VPOPCNTDQ (1 << 14) 431 #define BX_CPUID_EXT4_RESERVED15 (1 << 15) 432 #define BX_CPUID_EXT4_LA57 (1 << 16) 433 #define BX_CPUID_EXT4_RESERVED17 (1 << 17) 434 #define BX_CPUID_EXT4_RESERVED18 (1 << 18) 435 #define BX_CPUID_EXT4_RESERVED19 (1 << 19) 436 #define BX_CPUID_EXT4_RESERVED20 (1 << 20) 437 #define BX_CPUID_EXT4_RESERVED21 (1 << 21) 438 #define BX_CPUID_EXT4_RDPID (1 << 22) 439 #define BX_CPUID_EXT4_KEYLOCKER (1 << 23) 440 #define BX_CPUID_EXT4_RESERVED24 (1 << 24) 441 #define BX_CPUID_EXT4_CLDEMOTE (1 << 25) 442 #define BX_CPUID_EXT4_RESERVED26 (1 << 26) 443 #define BX_CPUID_EXT4_MOVDIRI (1 << 27) 444 #define BX_CPUID_EXT4_MOVDIR64B (1 << 28) 445 #define BX_CPUID_EXT4_ENQCMD (1 << 29) 446 #define BX_CPUID_EXT4_SGX_LAUNCH_CONFIG (1 << 30) 447 #define BX_CPUID_EXT4_PKS (1 << 31) 448 449 // CPUID defines - EXT5 features CPUID[0x00000007].EDX 450 // ----------------------------- 451 // [1:0] reserved 452 // [2:2] AVX512 4VNNIW instructions support 453 // [3:3] AVX512 4FMAPS instructions support 454 // [4:4] Support of Fast REP MOV instructions with short length 455 // [5:5] UINTR: User interrupts support 456 // [7:6] reserved 457 // [8:8] AVX512 VP2INTERSECT instructions support 458 // [9:9] reserved 459 // [10:10] MD clear 460 // [13:11] reserved 461 // [14:14] SERIALIZE instruction support 462 // [15:15] Hybrid 463 // [16:16] TSXLDTRK: TSX suspent load tracking support 464 // [19:17] reserved 465 // [20:20] CET IBT: Support CET indirect branch tracking 466 // [21:21] reserved 467 // [22:22] AMX BF16 support 468 // [23:23] AVX512_FP16 instructions support 469 // [24:24] AMX TILE architecture support 470 // [25:25] AMX INT8 support 471 // [26:26] IBRS and IBPB: Indirect branch restricted speculation (SCA) 472 // [27:27] STIBP: Single Thread Indirect Branch Predictors supported (SCA) 473 // [28:28] L1D_FLUSH supported (SCA) 474 // [29:29] MSR_IA32_ARCH_CAPABILITIES supported (SCA) 475 // [30:30] MSR_IA32_CORE_CAPABILITIES supported (SCA) 476 // [31:31] SSBD: Speculative Store Bypass Disable supported (SCA) 477 478 #define BX_CPUID_EXT5_RESERVED0 (1 << 0) 479 #define BX_CPUID_EXT5_RESERVED1 (1 << 1) 480 #define BX_CPUID_EXT5_AVX512_4VNNIW (1 << 2) 481 #define BX_CPUID_EXT5_AVX512_4FMAPS (1 << 3) 482 #define BX_CPUID_EXT5_FAST_SHORT_REP_MOV (1 << 4) 483 #define BX_CPUID_EXT5_UINTR (1 << 5) 484 #define BX_CPUID_EXT5_RESERVED6 (1 << 6) 485 #define BX_CPUID_EXT5_RESERVED7 (1 << 7) 486 #define BX_CPUID_EXT5_AVX512_VPINTERSECT (1 << 8) 487 #define BX_CPUID_EXT5_RESERVED9 (1 << 9) 488 #define BX_CPUID_EXT5_MD_CLEAR (1 << 10) 489 #define BX_CPUID_EXT5_RESERVED11 (1 << 11) 490 #define BX_CPUID_EXT5_RESERVED12 (1 << 12) 491 #define BX_CPUID_EXT5_RESERVED13 (1 << 13) 492 #define BX_CPUID_EXT5_SERIALIZE (1 << 14) 493 #define BX_CPUID_EXT5_HYBRID (1 << 15) 494 #define BX_CPUID_EXT5_TSXLDTRK (1 << 16) 495 #define BX_CPUID_EXT5_RESERVED17 (1 << 17) 496 #define BX_CPUID_EXT5_RESERVED18 (1 << 18) 497 #define BX_CPUID_EXT5_RESERVED19 (1 << 19) 498 #define BX_CPUID_EXT5_CET_IBT (1 << 20) 499 #define BX_CPUID_EXT5_RESERVED21 (1 << 21) 500 #define BX_CPUID_EXT5_AMX_BF16 (1 << 22) 501 #define BX_CPUID_EXT5_AVX512_FP16 (1 << 23) 502 #define BX_CPUID_EXT5_AMX_TILE (1 << 24) 503 #define BX_CPUID_EXT5_AMX_INT8 (1 << 25) 504 #define BX_CPUID_EXT5_SCA_IBRS_IBPB (1 << 26) 505 #define BX_CPUID_EXT5_SCA_STIBP (1 << 27) 506 #define BX_CPUID_EXT5_L1D_FLUSH (1 << 28) 507 #define BX_CPUID_EXT5_ARCH_CAPABILITIES_MSR (1 << 29) 508 #define BX_CPUID_EXT5_CORE_CAPABILITIES_MSR (1 << 30) 509 #define BX_CPUID_EXT5_SCA_SSBD (1 << 31) 510 511 // CPUID defines - STD2 features CPUID[0x80000001].EDX 512 // ----------------------------- 513 514 // ... 515 #define BX_CPUID_STD2_SYSCALL_SYSRET (1 << 11) 516 // ... 517 #define BX_CPUID_STD2_NX (1 << 20) 518 #define BX_CPUID_STD2_RESERVED21 (1 << 21) 519 #define BX_CPUID_STD2_AMD_MMX_EXT (1 << 22) 520 #define BX_CPUID_STD2_RESERVED23 (1 << 23) 521 #define BX_CPUID_STD2_RESERVED24 (1 << 24) 522 #define BX_CPUID_STD2_FFXSR (1 << 25) 523 #define BX_CPUID_STD2_1G_PAGES (1 << 26) 524 #define BX_CPUID_STD2_RDTSCP (1 << 27) 525 #define BX_CPUID_STD2_RESERVED28 (1 << 28) 526 #define BX_CPUID_STD2_LONG_MODE (1 << 29) 527 #define BX_CPUID_STD2_3DNOW_EXT (1 << 30) 528 #define BX_CPUID_STD2_3DNOW (1 << 31) 529 530 // CPUID defines - EXT2 features CPUID[0x80000001].ECX 531 // ----------------------------- 532 533 // [0:0] LAHF/SAHF instructions support in 64-bit mode 534 // [1:1] CMP_Legacy: Core multi-processing legacy mode (AMD) 535 // [2:2] SVM: Secure Virtual Machine (AMD) 536 // [3:3] Extended APIC Space 537 // [4:4] AltMovCR8: LOCK MOV CR0 means MOV CR8 538 // [5:5] LZCNT: LZCNT instruction support 539 // [6:6] SSE4A: SSE4A Instructions support 540 // [7:7] Misaligned SSE support 541 // [8:8] PREFETCHW: PREFETCHW instruction support 542 // [9:9] OSVW: OS visible workarounds (AMD) 543 // [10:10] IBS: Instruction based sampling 544 // [11:11] XOP: Extended Operations Support and XOP Prefix 545 // [12:12] SKINIT support 546 // [13:13] WDT: Watchdog timer support 547 // [14:14] reserved 548 // [15:15] LWP: Light weight profiling 549 // [16:16] FMA4: Four-operand FMA instructions support 550 // [17:17] Translation Cache Extensions (reserved?) 551 // [18:18] reserved 552 // [19:19] NodeId: Indicates support for NodeId MSR (0xc001100c) 553 // [20:20] reserved 554 // [21:21] TBM: trailing bit manipulation instruction support 555 // [22:22] Topology extensions support 556 // [23:23] PerfCtrExtCore: core performance counter extensions support 557 // [24:24] PerfCtrExtNB: NB performance counter extensions support 558 // [25:25] reserved 559 // [26:26] Data breakpoint extension. Indicates support for MSR 0xC0011027 and MSRs 0xC001101[B:9]. 560 // [27:27] Performance time-stamp counter. Indicates support for MSR 0xC0010280. 561 // [28:28] PerfCtrExtL2I: L2I performance counter extensions support. 562 // [29:29] MONITORX/MWAITX support 563 // [30:30] AddrMaskExt: address mask extension support for instruction breakpoint 564 // [31:31] reserved 565 566 #define BX_CPUID_EXT2_LAHF_SAHF (1 << 0) 567 #define BX_CPUID_EXT2_CMP_LEGACY (1 << 1) 568 #define BX_CPUID_EXT2_SVM (1 << 2) 569 #define BX_CPUID_EXT2_EXT_APIC_SPACE (1 << 3) 570 #define BX_CPUID_EXT2_ALT_MOV_CR8 (1 << 4) 571 #define BX_CPUID_EXT2_LZCNT (1 << 5) 572 #define BX_CPUID_EXT2_SSE4A (1 << 6) 573 #define BX_CPUID_EXT2_MISALIGNED_SSE (1 << 7) 574 #define BX_CPUID_EXT2_PREFETCHW (1 << 8) 575 #define BX_CPUID_EXT2_OSVW (1 << 9) 576 #define BX_CPUID_EXT2_IBS (1 << 10) 577 #define BX_CPUID_EXT2_XOP (1 << 11) 578 #define BX_CPUID_EXT2_SKINIT (1 << 12) 579 #define BX_CPUID_EXT2_WDT (1 << 13) 580 #define BX_CPUID_EXT2_RESERVED14 (1 << 14) 581 #define BX_CPUID_EXT2_LWP (1 << 15) 582 #define BX_CPUID_EXT2_FMA4 (1 << 16) 583 #define BX_CPUID_EXT2_TCE (1 << 17) 584 #define BX_CPUID_EXT2_RESERVED18 (1 << 18) 585 #define BX_CPUID_EXT2_NODEID (1 << 19) 586 #define BX_CPUID_EXT2_RESERVED20 (1 << 20) 587 #define BX_CPUID_EXT2_TBM (1 << 21) 588 #define BX_CPUID_EXT2_TOPOLOGY_EXTENSIONS (1 << 22) 589 #define BX_CPUID_EXT2_PERFCTR_EXT_CORE (1 << 23) 590 #define BX_CPUID_EXT2_PERFCTR_EXT_NB (1 << 24) 591 #define BX_CPUID_EXT2_RESERVED25 (1 << 25) 592 #define BX_CPUID_EXT2_DATA_BREAKPOINT_EXT (1 << 26) 593 #define BX_CPUID_EXT2_PERF_TSC (1 << 27) 594 #define BX_CPUID_EXT2_PERFCTR_EXT_L2I (1 << 28) 595 #define BX_CPUID_EXT2_MONITORX_MWAITX (1 << 29) 596 #define BX_CPUID_EXT2_CODEBP_ADDRMASK_EXT (1 << 30) 597 #define BX_CPUID_EXT2_RESERVED31 (1 << 31) 598 599 // CPUID defines - SVM features CPUID[0x8000000A].EDX 600 // ---------------------------- 601 602 // [0:0] NP - Nested paging support 603 // [1:1] LBR virtualization 604 // [2:2] SVM Lock 605 // [3:3] NRIPS - Next RIP save on VMEXIT 606 // [4:4] TscRate - MSR based TSC ratio control 607 // [5:5] VMCB Clean bits support 608 // [6:6] Flush by ASID support 609 // [7:7] Decode assists support 610 // [8:8] Reserved 611 // [9:9] Reserved 612 // [10:10] Pause filter support 613 // [11:11] Reserved 614 // [12:12] Pause filter threshold support 615 // [13:13] Advanced Virtual Interrupt Controller 616 // [14:14] Reserved 617 // [15:15] Nested Virtualization (virtualized VMLOAD and VMSAVE) Support 618 // [16:16] Virtual GIF 619 // [17:17] Guest Mode Execute Trap (CMET) 620 621 #define BX_CPUID_SVM_NESTED_PAGING (1 << 0) 622 #define BX_CPUID_SVM_LBR_VIRTUALIZATION (1 << 1) 623 #define BX_CPUID_SVM_SVM_LOCK (1 << 2) 624 #define BX_CPUID_SVM_NRIP_SAVE (1 << 3) 625 #define BX_CPUID_SVM_TSCRATE (1 << 4) 626 #define BX_CPUID_SVM_VMCB_CLEAN_BITS (1 << 5) 627 #define BX_CPUID_SVM_FLUSH_BY_ASID (1 << 6) 628 #define BX_CPUID_SVM_DECODE_ASSIST (1 << 7) 629 #define BX_CPUID_SVM_RESERVED8 (1 << 8) 630 #define BX_CPUID_SVM_RESERVED9 (1 << 9) 631 #define BX_CPUID_SVM_PAUSE_FILTER (1 << 10) 632 #define BX_CPUID_SVM_RESERVED11 (1 << 11) 633 #define BX_CPUID_SVM_PAUSE_FILTER_THRESHOLD (1 << 12) 634 #define BX_CPUID_SVM_AVIC (1 << 13) 635 #define BX_CPUID_SVM_RESERVED14 (1 << 14) 636 #define BX_CPUID_SVM_NESTED_VIRTUALIZATION (1 << 15) 637 #define BX_CPUID_SVM_VIRTUAL_GIF (1 << 16) 638 #define BX_CPUID_SVM_CMET (1 << 17) 639 640 #endif 641