/dports/devel/avr-gdb/gdb-7.3.1/opcodes/ |
H A D | s390-opc.c | 104 #define B_16 23 /* Base register starting at position 16 */ macro 254 #define INSTR_RIS_RURDI 6, { R_8,I8_32,U4_12,D_20,B_16,0 } /* e.g. cib */ 255 #define INSTR_RIS_R0RDI 6, { R_8,I8_32,D_20,B_16,0,0 } /* e.g. cibne */ 256 #define INSTR_RIS_RURDU 6, { R_8,U8_32,U4_12,D_20,B_16,0 } /* e.g. clib */ 257 #define INSTR_RIS_R0RDU 6, { R_8,U8_32,D_20,B_16,0,0 } /* e.g. clibne*/ 298 #define INSTR_RRS_RRRDU 6, { R_8,R_12,U4_32,D_20,B_16 } /* e.g. crb */ 299 #define INSTR_RRS_RRRD0 6, { R_8,R_12,D_20,B_16,0 } /* e.g. crbne */ 300 #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */ 301 #define INSTR_RSE_CCRD 6, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lmh */ 302 #define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */ [all …]
|
/dports/devel/gdb761/gdb-7.6.1/opcodes/ |
H A D | s390-opc.c | 140 #define B_16 37 /* Base register starting at position 16 */ macro 311 #define INSTR_RIS_RURDI 6, { R_8,I8_32,U4_12,D_20,B_16,0 } /* e.g. cib */ 312 #define INSTR_RIS_R0RDI 6, { R_8,I8_32,D_20,B_16,0,0 } /* e.g. cibne */ 313 #define INSTR_RIS_RURDU 6, { R_8,U8_32,U4_12,D_20,B_16,0 } /* e.g. clib */ 314 #define INSTR_RIS_R0RDU 6, { R_8,U8_32,D_20,B_16,0,0 } /* e.g. clibne*/ 384 #define INSTR_RRS_RRRDU 6, { R_8,R_12,U4_32,D_20,B_16 } /* e.g. crb */ 385 #define INSTR_RRS_RRRD0 6, { R_8,R_12,D_20,B_16,0 } /* e.g. crbne */ 386 #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */ 387 #define INSTR_RSE_RERERD 6, { RE_8,RE_12,D_20,B_16,0,0 } /* e.g. mvclu */ 432 #define INSTR_SMI_U0RDP 6, { U4_8,J16_32,D_20,B_16,0,0 } /* e.g. bpp */ [all …]
|
/dports/lang/gnatdroid-binutils-x86/binutils-2.27/opcodes/ |
H A D | s390-opc.c | 145 #define B_16 38 /* Base register starting at position 16 */ macro 324 #define INSTR_RIS_RURDI 6, { R_8,I8_32,U4_12,D_20,B_16,0 } /* e.g. cib */ 325 #define INSTR_RIS_R0RDI 6, { R_8,I8_32,D_20,B_16,0,0 } /* e.g. cibne */ 326 #define INSTR_RIS_RURDU 6, { R_8,U8_32,U4_12,D_20,B_16,0 } /* e.g. clib */ 327 #define INSTR_RIS_R0RDU 6, { R_8,U8_32,D_20,B_16,0,0 } /* e.g. clibne*/ 391 #define INSTR_RRS_RRRDU 6, { R_8,R_12,U4_32,D_20,B_16 } /* e.g. crb */ 392 #define INSTR_RRS_RRRD0 6, { R_8,R_12,D_20,B_16,0 } /* e.g. crbne */ 393 #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */ 394 #define INSTR_RSE_RERERD 6, { RE_8,RE_12,D_20,B_16,0,0 } /* e.g. mvclu */ 395 #define INSTR_RSE_CCRD 6, { C_8,C_12,D_20,B_16,0,0 } /* e.g. stctg */ [all …]
|
/dports/lang/gnatdroid-binutils/binutils-2.27/opcodes/ |
H A D | s390-opc.c | 145 #define B_16 38 /* Base register starting at position 16 */ macro 324 #define INSTR_RIS_RURDI 6, { R_8,I8_32,U4_12,D_20,B_16,0 } /* e.g. cib */ 325 #define INSTR_RIS_R0RDI 6, { R_8,I8_32,D_20,B_16,0,0 } /* e.g. cibne */ 326 #define INSTR_RIS_RURDU 6, { R_8,U8_32,U4_12,D_20,B_16,0 } /* e.g. clib */ 327 #define INSTR_RIS_R0RDU 6, { R_8,U8_32,D_20,B_16,0,0 } /* e.g. clibne*/ 391 #define INSTR_RRS_RRRDU 6, { R_8,R_12,U4_32,D_20,B_16 } /* e.g. crb */ 392 #define INSTR_RRS_RRRD0 6, { R_8,R_12,D_20,B_16,0 } /* e.g. crbne */ 393 #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */ 394 #define INSTR_RSE_RERERD 6, { RE_8,RE_12,D_20,B_16,0,0 } /* e.g. mvclu */ 395 #define INSTR_RSE_CCRD 6, { C_8,C_12,D_20,B_16,0,0 } /* e.g. stctg */ [all …]
|
/dports/devel/djgpp-binutils/binutils-2.17/opcodes/ |
H A D | s390-opc.c | 89 #define B_16 21 /* Base register starting at position 16 */ macro 219 #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */ 220 #define INSTR_RSE_CCRD 6, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lmh */ 221 #define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */ 222 #define INSTR_RSL_R0RD 6, { R_8,D_20,B_16,0,0,0 } /* e.g. tp */ 224 #define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */ 225 #define INSTR_RSY_RURD 6, { R_8,U4_12,D20_20,B_16,0,0 } /* e.g. icmh */ 226 #define INSTR_RSY_AARD 6, { A_8,A_12,D20_20,B_16,0,0 } /* e.g. lamy */ 227 #define INSTR_RSY_CCRD 6, { C_8,C_12,D20_20,B_16,0,0 } /* e.g. lamy */ 228 #define INSTR_RS_AARD 4, { A_8,A_12,D_20,B_16,0,0 } /* e.g. lam */ [all …]
|
/dports/devel/arm-elf-binutils/binutils-2.37/opcodes/ |
H A D | s390-opc.c | 145 #define B_16 38 /* Base register starting at position 16 */ macro 329 #define INSTR_RIS_RURDI 6, { R_8,I8_32,U4_12,D_20,B_16,0 } /* e.g. cib */ 330 #define INSTR_RIS_R0RDI 6, { R_8,I8_32,D_20,B_16,0,0 } /* e.g. cibne */ 331 #define INSTR_RIS_RURDU 6, { R_8,U8_32,U4_12,D_20,B_16,0 } /* e.g. clib */ 332 #define INSTR_RIS_R0RDU 6, { R_8,U8_32,D_20,B_16,0,0 } /* e.g. clibne*/ 399 #define INSTR_RRS_RRRDU 6, { R_8,R_12,U4_32,D_20,B_16 } /* e.g. crb */ 400 #define INSTR_RRS_RRRD0 6, { R_8,R_12,D_20,B_16,0 } /* e.g. crbne */ 401 #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */ 402 #define INSTR_RSE_RERERD 6, { RE_8,RE_12,D_20,B_16,0,0 } /* e.g. mvclu */ 403 #define INSTR_RSE_CCRD 6, { C_8,C_12,D_20,B_16,0,0 } /* e.g. stctg */ [all …]
|
/dports/devel/gdb/gdb-11.1/opcodes/ |
H A D | s390-opc.c | 145 #define B_16 38 /* Base register starting at position 16 */ macro 329 #define INSTR_RIS_RURDI 6, { R_8,I8_32,U4_12,D_20,B_16,0 } /* e.g. cib */ 330 #define INSTR_RIS_R0RDI 6, { R_8,I8_32,D_20,B_16,0,0 } /* e.g. cibne */ 331 #define INSTR_RIS_RURDU 6, { R_8,U8_32,U4_12,D_20,B_16,0 } /* e.g. clib */ 332 #define INSTR_RIS_R0RDU 6, { R_8,U8_32,D_20,B_16,0,0 } /* e.g. clibne*/ 399 #define INSTR_RRS_RRRDU 6, { R_8,R_12,U4_32,D_20,B_16 } /* e.g. crb */ 400 #define INSTR_RRS_RRRD0 6, { R_8,R_12,D_20,B_16,0 } /* e.g. crbne */ 401 #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */ 402 #define INSTR_RSE_RERERD 6, { RE_8,RE_12,D_20,B_16,0,0 } /* e.g. mvclu */ 403 #define INSTR_RSE_CCRD 6, { C_8,C_12,D_20,B_16,0,0 } /* e.g. stctg */ [all …]
|
/dports/devel/gnulibiberty/binutils-2.37/opcodes/ |
H A D | s390-opc.c | 145 #define B_16 38 /* Base register starting at position 16 */ macro 329 #define INSTR_RIS_RURDI 6, { R_8,I8_32,U4_12,D_20,B_16,0 } /* e.g. cib */ 330 #define INSTR_RIS_R0RDI 6, { R_8,I8_32,D_20,B_16,0,0 } /* e.g. cibne */ 331 #define INSTR_RIS_RURDU 6, { R_8,U8_32,U4_12,D_20,B_16,0 } /* e.g. clib */ 332 #define INSTR_RIS_R0RDU 6, { R_8,U8_32,D_20,B_16,0,0 } /* e.g. clibne*/ 399 #define INSTR_RRS_RRRDU 6, { R_8,R_12,U4_32,D_20,B_16 } /* e.g. crb */ 400 #define INSTR_RRS_RRRD0 6, { R_8,R_12,D_20,B_16,0 } /* e.g. crbne */ 401 #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */ 402 #define INSTR_RSE_RERERD 6, { RE_8,RE_12,D_20,B_16,0,0 } /* e.g. mvclu */ 403 #define INSTR_RSE_CCRD 6, { C_8,C_12,D_20,B_16,0,0 } /* e.g. stctg */ [all …]
|
/dports/devel/binutils/binutils-2.37/opcodes/ |
H A D | s390-opc.c | 145 #define B_16 38 /* Base register starting at position 16 */ macro 329 #define INSTR_RIS_RURDI 6, { R_8,I8_32,U4_12,D_20,B_16,0 } /* e.g. cib */ 330 #define INSTR_RIS_R0RDI 6, { R_8,I8_32,D_20,B_16,0,0 } /* e.g. cibne */ 331 #define INSTR_RIS_RURDU 6, { R_8,U8_32,U4_12,D_20,B_16,0 } /* e.g. clib */ 332 #define INSTR_RIS_R0RDU 6, { R_8,U8_32,D_20,B_16,0,0 } /* e.g. clibne*/ 399 #define INSTR_RRS_RRRDU 6, { R_8,R_12,U4_32,D_20,B_16 } /* e.g. crb */ 400 #define INSTR_RRS_RRRD0 6, { R_8,R_12,D_20,B_16,0 } /* e.g. crbne */ 401 #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */ 402 #define INSTR_RSE_RERERD 6, { RE_8,RE_12,D_20,B_16,0,0 } /* e.g. mvclu */ 403 #define INSTR_RSE_CCRD 6, { C_8,C_12,D_20,B_16,0,0 } /* e.g. stctg */ [all …]
|
/dports/devel/tigcc/tigcc-0.96.b8_10/gnu/binutils-2.16.1/opcodes/ |
H A D | s390-opc.c | 89 #define B_16 21 /* Base register starting at position 16 */ macro 209 #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */ 210 #define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */ 211 #define INSTR_RSL_R0RD 6, { R_8,D_20,B_16,0,0,0 } /* e.g. tp */ 213 #define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */ 214 #define INSTR_RSY_RURD 6, { R_8,U4_12,D20_20,B_16,0,0 } /* e.g. icmh */ 215 #define INSTR_RSY_AARD 6, { A_8,A_12,D20_20,B_16,0,0 } /* e.g. lamy */ 216 #define INSTR_RS_AARD 4, { A_8,A_12,D_20,B_16,0,0 } /* e.g. lam */ 217 #define INSTR_RS_CCRD 4, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lctl */ 218 #define INSTR_RS_R0RD 4, { R_8,D_20,B_16,0,0,0 } /* e.g. sll */ [all …]
|
/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/binutils/opcodes/ |
H A D | s390-opc.c | 89 #define B_16 21 /* Base register starting at position 16 */ macro 209 #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */ 210 #define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */ 211 #define INSTR_RSL_R0RD 6, { R_8,D_20,B_16,0,0,0 } /* e.g. tp */ 213 #define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */ 214 #define INSTR_RSY_RURD 6, { R_8,U4_12,D20_20,B_16,0,0 } /* e.g. icmh */ 215 #define INSTR_RSY_AARD 6, { A_8,A_12,D20_20,B_16,0,0 } /* e.g. lamy */ 216 #define INSTR_RS_AARD 4, { A_8,A_12,D_20,B_16,0,0 } /* e.g. lam */ 217 #define INSTR_RS_CCRD 4, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lctl */ 218 #define INSTR_RS_R0RD 4, { R_8,D_20,B_16,0,0,0 } /* e.g. sll */ [all …]
|
/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/binutils/opcodes/ |
H A D | s390-opc.c | 89 #define B_16 21 /* Base register starting at position 16 */ macro 209 #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */ 210 #define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */ 211 #define INSTR_RSL_R0RD 6, { R_8,D_20,B_16,0,0,0 } /* e.g. tp */ 213 #define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */ 214 #define INSTR_RSY_RURD 6, { R_8,U4_12,D20_20,B_16,0,0 } /* e.g. icmh */ 215 #define INSTR_RSY_AARD 6, { A_8,A_12,D20_20,B_16,0,0 } /* e.g. lamy */ 216 #define INSTR_RS_AARD 4, { A_8,A_12,D_20,B_16,0,0 } /* e.g. lam */ 217 #define INSTR_RS_CCRD 4, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lctl */ 218 #define INSTR_RS_R0RD 4, { R_8,D_20,B_16,0,0,0 } /* e.g. sll */ [all …]
|
/dports/multimedia/v4l-utils/linux-5.13-rc2/arch/s390/kernel/ |
H A D | dis.c | 79 B_16, /* Base register starting at position 16 */ enumerator 141 [B_16] = { 4, 16, OPERAND_BASE | OPERAND_GPR }, 257 [INSTR_RSL_R0RD] = { D_20, L4_8, B_16, 0, 0, 0 }, 264 [INSTR_RS_AARD] = { A_8, A_12, D_20, B_16, 0, 0 }, 265 [INSTR_RS_CCRD] = { C_8, C_12, D_20, B_16, 0, 0 }, 266 [INSTR_RS_R0RD] = { R_8, D_20, B_16, 0, 0, 0 }, 267 [INSTR_RS_RRRD] = { R_8, R_12, D_20, B_16, 0, 0 }, 269 [INSTR_RXE_FRRD] = { F_8, D_20, X_12, B_16, 0, 0 }, 282 [INSTR_SI_RD] = { D_20, B_16, 0, 0, 0, 0 }, 283 [INSTR_SI_URD] = { D_20, B_16, U8_8, 0, 0, 0 }, [all …]
|
/dports/multimedia/v4l_compat/linux-5.13-rc2/arch/s390/kernel/ |
H A D | dis.c | 79 B_16, /* Base register starting at position 16 */ enumerator 141 [B_16] = { 4, 16, OPERAND_BASE | OPERAND_GPR }, 257 [INSTR_RSL_R0RD] = { D_20, L4_8, B_16, 0, 0, 0 }, 264 [INSTR_RS_AARD] = { A_8, A_12, D_20, B_16, 0, 0 }, 265 [INSTR_RS_CCRD] = { C_8, C_12, D_20, B_16, 0, 0 }, 266 [INSTR_RS_R0RD] = { R_8, D_20, B_16, 0, 0, 0 }, 267 [INSTR_RS_RRRD] = { R_8, R_12, D_20, B_16, 0, 0 }, 269 [INSTR_RXE_FRRD] = { F_8, D_20, X_12, B_16, 0, 0 }, 282 [INSTR_SI_RD] = { D_20, B_16, 0, 0, 0, 0 }, 283 [INSTR_SI_URD] = { D_20, B_16, U8_8, 0, 0, 0 }, [all …]
|
/dports/multimedia/libv4l/linux-5.13-rc2/arch/s390/kernel/ |
H A D | dis.c | 79 B_16, /* Base register starting at position 16 */ enumerator 141 [B_16] = { 4, 16, OPERAND_BASE | OPERAND_GPR }, 257 [INSTR_RSL_R0RD] = { D_20, L4_8, B_16, 0, 0, 0 }, 264 [INSTR_RS_AARD] = { A_8, A_12, D_20, B_16, 0, 0 }, 265 [INSTR_RS_CCRD] = { C_8, C_12, D_20, B_16, 0, 0 }, 266 [INSTR_RS_R0RD] = { R_8, D_20, B_16, 0, 0, 0 }, 267 [INSTR_RS_RRRD] = { R_8, R_12, D_20, B_16, 0, 0 }, 269 [INSTR_RXE_FRRD] = { F_8, D_20, X_12, B_16, 0, 0 }, 282 [INSTR_SI_RD] = { D_20, B_16, 0, 0, 0, 0 }, 283 [INSTR_SI_URD] = { D_20, B_16, U8_8, 0, 0, 0 }, [all …]
|
/dports/emulators/qemu/qemu-6.2.0/disas/ |
H A D | s390.c | 526 #define B_16 21 /* Base register starting at position 16 */ macro 688 #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */ 689 #define INSTR_RSE_CCRD 6, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lmh */ 690 #define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */ 691 #define INSTR_RSL_R0RD 6, { R_8,D_20,B_16,0,0,0 } /* e.g. tp */ 693 #define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */ 694 #define INSTR_RSY_RURD 6, { R_8,U4_12,D20_20,B_16,0,0 } /* e.g. icmh */ 823 #define INSTR_RXY_URRD 6, { U8_8, D20_20, X_12, B_16, 0, 0 } 826 #define INSTR_SIL_DRI 6, { D_20, B_16, I16_32, 0, 0, 0 } 829 #define INSTR_RSY_MRRD 6, { M4_12, R_8, D20_20, B_16, 0, 0 } [all …]
|
/dports/emulators/qemu42/qemu-4.2.1/disas/ |
H A D | s390.c | 526 #define B_16 21 /* Base register starting at position 16 */ macro 688 #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */ 689 #define INSTR_RSE_CCRD 6, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lmh */ 690 #define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */ 691 #define INSTR_RSL_R0RD 6, { R_8,D_20,B_16,0,0,0 } /* e.g. tp */ 693 #define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */ 694 #define INSTR_RSY_RURD 6, { R_8,U4_12,D20_20,B_16,0,0 } /* e.g. icmh */ 823 #define INSTR_RXY_URRD 6, { U8_8, D20_20, X_12, B_16, 0, 0 } 826 #define INSTR_SIL_DRI 6, { D_20, B_16, I16_32, 0, 0, 0 } 829 #define INSTR_RSY_MRRD 6, { M4_12, R_8, D20_20, B_16, 0, 0 } [all …]
|
/dports/emulators/qemu5/qemu-5.2.0/disas/ |
H A D | s390.c | 526 #define B_16 21 /* Base register starting at position 16 */ macro 688 #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */ 689 #define INSTR_RSE_CCRD 6, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lmh */ 690 #define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */ 691 #define INSTR_RSL_R0RD 6, { R_8,D_20,B_16,0,0,0 } /* e.g. tp */ 693 #define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */ 694 #define INSTR_RSY_RURD 6, { R_8,U4_12,D20_20,B_16,0,0 } /* e.g. icmh */ 823 #define INSTR_RXY_URRD 6, { U8_8, D20_20, X_12, B_16, 0, 0 } 826 #define INSTR_SIL_DRI 6, { D_20, B_16, I16_32, 0, 0, 0 } 829 #define INSTR_RSY_MRRD 6, { M4_12, R_8, D20_20, B_16, 0, 0 } [all …]
|
/dports/emulators/qemu60/qemu-6.0.0/disas/ |
H A D | s390.c | 526 #define B_16 21 /* Base register starting at position 16 */ macro 688 #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */ 689 #define INSTR_RSE_CCRD 6, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lmh */ 690 #define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */ 691 #define INSTR_RSL_R0RD 6, { R_8,D_20,B_16,0,0,0 } /* e.g. tp */ 693 #define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */ 694 #define INSTR_RSY_RURD 6, { R_8,U4_12,D20_20,B_16,0,0 } /* e.g. icmh */ 823 #define INSTR_RXY_URRD 6, { U8_8, D20_20, X_12, B_16, 0, 0 } 826 #define INSTR_SIL_DRI 6, { D_20, B_16, I16_32, 0, 0, 0 } 829 #define INSTR_RSY_MRRD 6, { M4_12, R_8, D20_20, B_16, 0, 0 } [all …]
|
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/disas/ |
H A D | s390.c | 527 #define B_16 21 /* Base register starting at position 16 */ macro 689 #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */ 690 #define INSTR_RSE_CCRD 6, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lmh */ 691 #define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */ 692 #define INSTR_RSL_R0RD 6, { R_8,D_20,B_16,0,0,0 } /* e.g. tp */ 694 #define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */ 695 #define INSTR_RSY_RURD 6, { R_8,U4_12,D20_20,B_16,0,0 } /* e.g. icmh */ 824 #define INSTR_RXY_URRD 6, { U8_8, D20_20, X_12, B_16, 0, 0 } 827 #define INSTR_SIL_DRI 6, { D_20, B_16, I16_32, 0, 0, 0 } 830 #define INSTR_RSY_MRRD 6, { M4_12, R_8, D20_20, B_16, 0, 0 } [all …]
|
/dports/emulators/qemu-utils/qemu-4.2.1/disas/ |
H A D | s390.c | 526 #define B_16 21 /* Base register starting at position 16 */ macro 688 #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */ 689 #define INSTR_RSE_CCRD 6, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lmh */ 690 #define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */ 691 #define INSTR_RSL_R0RD 6, { R_8,D_20,B_16,0,0,0 } /* e.g. tp */ 693 #define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */ 694 #define INSTR_RSY_RURD 6, { R_8,U4_12,D20_20,B_16,0,0 } /* e.g. icmh */ 823 #define INSTR_RXY_URRD 6, { U8_8, D20_20, X_12, B_16, 0, 0 } 826 #define INSTR_SIL_DRI 6, { D_20, B_16, I16_32, 0, 0, 0 } 829 #define INSTR_RSY_MRRD 6, { M4_12, R_8, D20_20, B_16, 0, 0 } [all …]
|
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/disas/ |
H A D | s390.c | 526 #define B_16 21 /* Base register starting at position 16 */ macro 688 #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */ 689 #define INSTR_RSE_CCRD 6, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lmh */ 690 #define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */ 691 #define INSTR_RSL_R0RD 6, { R_8,D_20,B_16,0,0,0 } /* e.g. tp */ 693 #define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */ 694 #define INSTR_RSY_RURD 6, { R_8,U4_12,D20_20,B_16,0,0 } /* e.g. icmh */ 823 #define INSTR_RXY_URRD 6, { U8_8, D20_20, X_12, B_16, 0, 0 } 826 #define INSTR_SIL_DRI 6, { D_20, B_16, I16_32, 0, 0, 0 } 829 #define INSTR_RSY_MRRD 6, { M4_12, R_8, D20_20, B_16, 0, 0 } [all …]
|
/dports/emulators/qemu-guest-agent/qemu-5.0.1/disas/ |
H A D | s390.c | 526 #define B_16 21 /* Base register starting at position 16 */ macro 688 #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */ 689 #define INSTR_RSE_CCRD 6, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lmh */ 690 #define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */ 691 #define INSTR_RSL_R0RD 6, { R_8,D_20,B_16,0,0,0 } /* e.g. tp */ 693 #define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */ 694 #define INSTR_RSY_RURD 6, { R_8,U4_12,D20_20,B_16,0,0 } /* e.g. icmh */ 823 #define INSTR_RXY_URRD 6, { U8_8, D20_20, X_12, B_16, 0, 0 } 826 #define INSTR_SIL_DRI 6, { D_20, B_16, I16_32, 0, 0, 0 } 829 #define INSTR_RSY_MRRD 6, { M4_12, R_8, D20_20, B_16, 0, 0 } [all …]
|
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/disas/ |
H A D | s390.c | 526 #define B_16 21 /* Base register starting at position 16 */ macro 688 #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */ 689 #define INSTR_RSE_CCRD 6, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lmh */ 690 #define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */ 691 #define INSTR_RSL_R0RD 6, { R_8,D_20,B_16,0,0,0 } /* e.g. tp */ 693 #define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */ 694 #define INSTR_RSY_RURD 6, { R_8,U4_12,D20_20,B_16,0,0 } /* e.g. icmh */ 823 #define INSTR_RXY_URRD 6, { U8_8, D20_20, X_12, B_16, 0, 0 } 826 #define INSTR_SIL_DRI 6, { D_20, B_16, I16_32, 0, 0, 0 } 829 #define INSTR_RSY_MRRD 6, { M4_12, R_8, D20_20, B_16, 0, 0 } [all …]
|
/dports/emulators/x49gp/x49gp/x49gp-code/qemu/qemu-git/ |
H A D | s390-dis.c | 479 #define B_16 21 /* Base register starting at position 16 */ macro 621 #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */ 622 #define INSTR_RSE_CCRD 6, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lmh */ 623 #define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */ 624 #define INSTR_RSL_R0RD 6, { R_8,D_20,B_16,0,0,0 } /* e.g. tp */ 626 #define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */ 627 #define INSTR_RSY_RURD 6, { R_8,U4_12,D20_20,B_16,0,0 } /* e.g. icmh */ 628 #define INSTR_RSY_AARD 6, { A_8,A_12,D20_20,B_16,0,0 } /* e.g. lamy */ 629 #define INSTR_RSY_CCRD 6, { C_8,C_12,D20_20,B_16,0,0 } /* e.g. lamy */ 630 #define INSTR_RS_AARD 4, { A_8,A_12,D_20,B_16,0,0 } /* e.g. lam */ [all …]
|