/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/Transforms/InstCombine/ |
H A D | add-sitofp.ll | 50 ; CHECK-NEXT: [[B_AND:%.*]] = and i32 [[B:%.*]], 1073741823 51 ; CHECK-NEXT: [[ADDCONV:%.*]] = add nuw nsw i32 [[A_AND]], [[B_AND]] 69 ; CHECK-NEXT: [[B_AND:%.*]] = and i32 [[B:%.*]], 1073741823 71 ; CHECK-NEXT: [[B_AND_FP:%.*]] = sitofp i32 [[B_AND]] to float 107 ; CHECK-NEXT: [[B_AND:%.*]] = and <4 x i32> [[B:%.*]], <i32 1073741823, i32 1073741823, i32 1073… 108 ; CHECK-NEXT: [[ADDCONV:%.*]] = add nuw nsw <4 x i32> [[A_AND]], [[B_AND]] 126 ; CHECK-NEXT: [[B_AND:%.*]] = and <4 x i32> [[B:%.*]], <i32 1073741823, i32 1073741823, i32 1073… 128 ; CHECK-NEXT: [[B_AND_FP:%.*]] = sitofp <4 x i32> [[B_AND]] to <4 x float>
|
/dports/devel/llvm11/llvm-11.0.1.src/test/Transforms/InstCombine/ |
H A D | add-sitofp.ll | 50 ; CHECK-NEXT: [[B_AND:%.*]] = and i32 [[B:%.*]], 1073741823 51 ; CHECK-NEXT: [[ADDCONV:%.*]] = add nuw nsw i32 [[A_AND]], [[B_AND]] 69 ; CHECK-NEXT: [[B_AND:%.*]] = and i32 [[B:%.*]], 1073741823 71 ; CHECK-NEXT: [[B_AND_FP:%.*]] = sitofp i32 [[B_AND]] to float 107 ; CHECK-NEXT: [[B_AND:%.*]] = and <4 x i32> [[B:%.*]], <i32 1073741823, i32 1073741823, i32 1073… 108 ; CHECK-NEXT: [[ADDCONV:%.*]] = add nuw nsw <4 x i32> [[A_AND]], [[B_AND]] 126 ; CHECK-NEXT: [[B_AND:%.*]] = and <4 x i32> [[B:%.*]], <i32 1073741823, i32 1073741823, i32 1073… 128 ; CHECK-NEXT: [[B_AND_FP:%.*]] = sitofp <4 x i32> [[B_AND]] to <4 x float>
|
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/Transforms/InstCombine/ |
H A D | add-sitofp.ll | 50 ; CHECK-NEXT: [[B_AND:%.*]] = and i32 [[B:%.*]], 1073741823 51 ; CHECK-NEXT: [[ADDCONV:%.*]] = add nuw nsw i32 [[A_AND]], [[B_AND]] 69 ; CHECK-NEXT: [[B_AND:%.*]] = and i32 [[B:%.*]], 1073741823 71 ; CHECK-NEXT: [[B_AND_FP:%.*]] = sitofp i32 [[B_AND]] to float 107 ; CHECK-NEXT: [[B_AND:%.*]] = and <4 x i32> [[B:%.*]], <i32 1073741823, i32 1073741823, i32 1073… 108 ; CHECK-NEXT: [[ADDCONV:%.*]] = add nuw nsw <4 x i32> [[A_AND]], [[B_AND]] 126 ; CHECK-NEXT: [[B_AND:%.*]] = and <4 x i32> [[B:%.*]], <i32 1073741823, i32 1073741823, i32 1073… 128 ; CHECK-NEXT: [[B_AND_FP:%.*]] = sitofp <4 x i32> [[B_AND]] to <4 x float>
|
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/Transforms/InstCombine/ |
H A D | add-sitofp.ll | 50 ; CHECK-NEXT: [[B_AND:%.*]] = and i32 [[B:%.*]], 1073741823 51 ; CHECK-NEXT: [[ADDCONV:%.*]] = add nuw nsw i32 [[A_AND]], [[B_AND]] 69 ; CHECK-NEXT: [[B_AND:%.*]] = and i32 [[B:%.*]], 1073741823 71 ; CHECK-NEXT: [[B_AND_FP:%.*]] = sitofp i32 [[B_AND]] to float 107 ; CHECK-NEXT: [[B_AND:%.*]] = and <4 x i32> [[B:%.*]], <i32 1073741823, i32 1073741823, i32 1073… 108 ; CHECK-NEXT: [[ADDCONV:%.*]] = add nuw nsw <4 x i32> [[A_AND]], [[B_AND]] 126 ; CHECK-NEXT: [[B_AND:%.*]] = and <4 x i32> [[B:%.*]], <i32 1073741823, i32 1073741823, i32 1073… 128 ; CHECK-NEXT: [[B_AND_FP:%.*]] = sitofp <4 x i32> [[B_AND]] to <4 x float>
|
/dports/devel/llvm10/llvm-10.0.1.src/test/Transforms/InstCombine/ |
H A D | add-sitofp.ll | 50 ; CHECK-NEXT: [[B_AND:%.*]] = and i32 [[B:%.*]], 1073741823 51 ; CHECK-NEXT: [[ADDCONV:%.*]] = add nuw nsw i32 [[A_AND]], [[B_AND]] 69 ; CHECK-NEXT: [[B_AND:%.*]] = and i32 [[B:%.*]], 1073741823 71 ; CHECK-NEXT: [[B_AND_FP:%.*]] = sitofp i32 [[B_AND]] to float 107 ; CHECK-NEXT: [[B_AND:%.*]] = and <4 x i32> [[B:%.*]], <i32 1073741823, i32 1073741823, i32 1073… 108 ; CHECK-NEXT: [[ADDCONV:%.*]] = add nuw nsw <4 x i32> [[A_AND]], [[B_AND]] 126 ; CHECK-NEXT: [[B_AND:%.*]] = and <4 x i32> [[B:%.*]], <i32 1073741823, i32 1073741823, i32 1073… 128 ; CHECK-NEXT: [[B_AND_FP:%.*]] = sitofp <4 x i32> [[B_AND]] to <4 x float>
|
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/Transforms/InstCombine/ |
H A D | add-sitofp.ll | 50 ; CHECK-NEXT: [[B_AND:%.*]] = and i32 [[B:%.*]], 1073741823 51 ; CHECK-NEXT: [[ADDCONV:%.*]] = add nuw nsw i32 [[A_AND]], [[B_AND]] 69 ; CHECK-NEXT: [[B_AND:%.*]] = and i32 [[B:%.*]], 1073741823 71 ; CHECK-NEXT: [[B_AND_FP:%.*]] = sitofp i32 [[B_AND]] to float 107 ; CHECK-NEXT: [[B_AND:%.*]] = and <4 x i32> [[B:%.*]], <i32 1073741823, i32 1073741823, i32 1073… 108 ; CHECK-NEXT: [[ADDCONV:%.*]] = add nuw nsw <4 x i32> [[A_AND]], [[B_AND]] 126 ; CHECK-NEXT: [[B_AND:%.*]] = and <4 x i32> [[B:%.*]], <i32 1073741823, i32 1073741823, i32 1073… 128 ; CHECK-NEXT: [[B_AND_FP:%.*]] = sitofp <4 x i32> [[B_AND]] to <4 x float>
|
/dports/devel/llvm90/llvm-9.0.1.src/test/Transforms/InstCombine/ |
H A D | add-sitofp.ll | 50 ; CHECK-NEXT: [[B_AND:%.*]] = and i32 [[B:%.*]], 1073741823 51 ; CHECK-NEXT: [[ADDCONV:%.*]] = add nuw nsw i32 [[A_AND]], [[B_AND]] 69 ; CHECK-NEXT: [[B_AND:%.*]] = and i32 [[B:%.*]], 1073741823 71 ; CHECK-NEXT: [[B_AND_FP:%.*]] = sitofp i32 [[B_AND]] to float 107 ; CHECK-NEXT: [[B_AND:%.*]] = and <4 x i32> [[B:%.*]], <i32 1073741823, i32 1073741823, i32 1073… 108 ; CHECK-NEXT: [[ADDCONV:%.*]] = add nuw nsw <4 x i32> [[A_AND]], [[B_AND]] 126 ; CHECK-NEXT: [[B_AND:%.*]] = and <4 x i32> [[B:%.*]], <i32 1073741823, i32 1073741823, i32 1073… 128 ; CHECK-NEXT: [[B_AND_FP:%.*]] = sitofp <4 x i32> [[B_AND]] to <4 x float>
|
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/Transforms/InstCombine/ |
H A D | add-sitofp.ll | 50 ; CHECK-NEXT: [[B_AND:%.*]] = and i32 [[B:%.*]], 1073741823 51 ; CHECK-NEXT: [[ADDCONV:%.*]] = add nuw nsw i32 [[A_AND]], [[B_AND]] 69 ; CHECK-NEXT: [[B_AND:%.*]] = and i32 [[B:%.*]], 1073741823 71 ; CHECK-NEXT: [[B_AND_FP:%.*]] = sitofp i32 [[B_AND]] to float 107 ; CHECK-NEXT: [[B_AND:%.*]] = and <4 x i32> [[B:%.*]], <i32 1073741823, i32 1073741823, i32 1073… 108 ; CHECK-NEXT: [[ADDCONV:%.*]] = add nuw nsw <4 x i32> [[A_AND]], [[B_AND]] 126 ; CHECK-NEXT: [[B_AND:%.*]] = and <4 x i32> [[B:%.*]], <i32 1073741823, i32 1073741823, i32 1073… 128 ; CHECK-NEXT: [[B_AND_FP:%.*]] = sitofp <4 x i32> [[B_AND]] to <4 x float>
|
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/Transforms/InstCombine/ |
H A D | add-sitofp.ll | 50 ; CHECK-NEXT: [[B_AND:%.*]] = and i32 [[B:%.*]], 1073741823 51 ; CHECK-NEXT: [[ADDCONV:%.*]] = add nuw nsw i32 [[A_AND]], [[B_AND]] 69 ; CHECK-NEXT: [[B_AND:%.*]] = and i32 [[B:%.*]], 1073741823 71 ; CHECK-NEXT: [[B_AND_FP:%.*]] = sitofp i32 [[B_AND]] to float 107 ; CHECK-NEXT: [[B_AND:%.*]] = and <4 x i32> [[B:%.*]], <i32 1073741823, i32 1073741823, i32 1073… 108 ; CHECK-NEXT: [[ADDCONV:%.*]] = add nuw nsw <4 x i32> [[A_AND]], [[B_AND]] 126 ; CHECK-NEXT: [[B_AND:%.*]] = and <4 x i32> [[B:%.*]], <i32 1073741823, i32 1073741823, i32 1073… 128 ; CHECK-NEXT: [[B_AND_FP:%.*]] = sitofp <4 x i32> [[B_AND]] to <4 x float>
|
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/Transforms/InstCombine/ |
H A D | add-sitofp.ll | 50 ; CHECK-NEXT: [[B_AND:%.*]] = and i32 [[B:%.*]], 1073741823 51 ; CHECK-NEXT: [[ADDCONV:%.*]] = add nuw nsw i32 [[A_AND]], [[B_AND]] 69 ; CHECK-NEXT: [[B_AND:%.*]] = and i32 [[B:%.*]], 1073741823 71 ; CHECK-NEXT: [[B_AND_FP:%.*]] = sitofp i32 [[B_AND]] to float 107 ; CHECK-NEXT: [[B_AND:%.*]] = and <4 x i32> [[B:%.*]], <i32 1073741823, i32 1073741823, i32 1073… 108 ; CHECK-NEXT: [[ADDCONV:%.*]] = add nuw nsw <4 x i32> [[A_AND]], [[B_AND]] 126 ; CHECK-NEXT: [[B_AND:%.*]] = and <4 x i32> [[B:%.*]], <i32 1073741823, i32 1073741823, i32 1073… 128 ; CHECK-NEXT: [[B_AND_FP:%.*]] = sitofp <4 x i32> [[B_AND]] to <4 x float>
|
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/Transforms/InstCombine/ |
H A D | add-sitofp.ll | 50 ; CHECK-NEXT: [[B_AND:%.*]] = and i32 [[B:%.*]], 1073741823 51 ; CHECK-NEXT: [[ADDCONV:%.*]] = add nuw nsw i32 [[A_AND]], [[B_AND]] 69 ; CHECK-NEXT: [[B_AND:%.*]] = and i32 [[B:%.*]], 1073741823 71 ; CHECK-NEXT: [[B_AND_FP:%.*]] = sitofp i32 [[B_AND]] to float 107 ; CHECK-NEXT: [[B_AND:%.*]] = and <4 x i32> [[B:%.*]], <i32 1073741823, i32 1073741823, i32 1073… 108 ; CHECK-NEXT: [[ADDCONV:%.*]] = add nuw nsw <4 x i32> [[A_AND]], [[B_AND]] 126 ; CHECK-NEXT: [[B_AND:%.*]] = and <4 x i32> [[B:%.*]], <i32 1073741823, i32 1073741823, i32 1073… 128 ; CHECK-NEXT: [[B_AND_FP:%.*]] = sitofp <4 x i32> [[B_AND]] to <4 x float>
|
/dports/devel/llvm80/llvm-8.0.1.src/test/Transforms/InstCombine/ |
H A D | add-sitofp.ll | 50 ; CHECK-NEXT: [[B_AND:%.*]] = and i32 [[B:%.*]], 1073741823 51 ; CHECK-NEXT: [[ADDCONV:%.*]] = add nuw nsw i32 [[A_AND]], [[B_AND]] 69 ; CHECK-NEXT: [[B_AND:%.*]] = and i32 [[B:%.*]], 1073741823 71 ; CHECK-NEXT: [[B_AND_FP:%.*]] = sitofp i32 [[B_AND]] to float 107 ; CHECK-NEXT: [[B_AND:%.*]] = and <4 x i32> [[B:%.*]], <i32 1073741823, i32 1073741823, i32 1073… 108 ; CHECK-NEXT: [[ADDCONV:%.*]] = add nuw nsw <4 x i32> [[A_AND]], [[B_AND]] 126 ; CHECK-NEXT: [[B_AND:%.*]] = and <4 x i32> [[B:%.*]], <i32 1073741823, i32 1073741823, i32 1073… 128 ; CHECK-NEXT: [[B_AND_FP:%.*]] = sitofp <4 x i32> [[B_AND]] to <4 x float>
|
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/Transforms/InstCombine/ |
H A D | add-sitofp.ll | 50 ; CHECK-NEXT: [[B_AND:%.*]] = and i32 [[B:%.*]], 1073741823 51 ; CHECK-NEXT: [[ADDCONV:%.*]] = add nuw nsw i32 [[A_AND]], [[B_AND]] 69 ; CHECK-NEXT: [[B_AND:%.*]] = and i32 [[B:%.*]], 1073741823 71 ; CHECK-NEXT: [[B_AND_FP:%.*]] = sitofp i32 [[B_AND]] to float 107 ; CHECK-NEXT: [[B_AND:%.*]] = and <4 x i32> [[B:%.*]], <i32 1073741823, i32 1073741823, i32 1073… 108 ; CHECK-NEXT: [[ADDCONV:%.*]] = add nuw nsw <4 x i32> [[A_AND]], [[B_AND]] 126 ; CHECK-NEXT: [[B_AND:%.*]] = and <4 x i32> [[B:%.*]], <i32 1073741823, i32 1073741823, i32 1073… 128 ; CHECK-NEXT: [[B_AND_FP:%.*]] = sitofp <4 x i32> [[B_AND]] to <4 x float>
|
/dports/devel/llvm70/llvm-7.0.1.src/test/Transforms/InstCombine/ |
H A D | add-sitofp.ll | 50 ; CHECK-NEXT: [[B_AND:%.*]] = and i32 [[B:%.*]], 1073741823 51 ; CHECK-NEXT: [[ADDCONV:%.*]] = add nuw nsw i32 [[A_AND]], [[B_AND]] 69 ; CHECK-NEXT: [[B_AND:%.*]] = and i32 [[B:%.*]], 1073741823 71 ; CHECK-NEXT: [[B_AND_FP:%.*]] = sitofp i32 [[B_AND]] to float 107 ; CHECK-NEXT: [[B_AND:%.*]] = and <4 x i32> [[B:%.*]], <i32 1073741823, i32 1073741823, i32 1073… 108 ; CHECK-NEXT: [[ADDCONV:%.*]] = add nuw nsw <4 x i32> [[A_AND]], [[B_AND]] 126 ; CHECK-NEXT: [[B_AND:%.*]] = and <4 x i32> [[B:%.*]], <i32 1073741823, i32 1073741823, i32 1073… 128 ; CHECK-NEXT: [[B_AND_FP:%.*]] = sitofp <4 x i32> [[B_AND]] to <4 x float>
|
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/Transforms/InstCombine/ |
H A D | add-sitofp.ll | 50 ; CHECK-NEXT: [[B_AND:%.*]] = and i32 [[B:%.*]], 1073741823 51 ; CHECK-NEXT: [[ADDCONV:%.*]] = add nuw nsw i32 [[A_AND]], [[B_AND]] 69 ; CHECK-NEXT: [[B_AND:%.*]] = and i32 [[B:%.*]], 1073741823 71 ; CHECK-NEXT: [[B_AND_FP:%.*]] = sitofp i32 [[B_AND]] to float 107 ; CHECK-NEXT: [[B_AND:%.*]] = and <4 x i32> [[B:%.*]], <i32 1073741823, i32 1073741823, i32 1073… 108 ; CHECK-NEXT: [[ADDCONV:%.*]] = add nuw nsw <4 x i32> [[A_AND]], [[B_AND]] 126 ; CHECK-NEXT: [[B_AND:%.*]] = and <4 x i32> [[B:%.*]], <i32 1073741823, i32 1073741823, i32 1073… 128 ; CHECK-NEXT: [[B_AND_FP:%.*]] = sitofp <4 x i32> [[B_AND]] to <4 x float>
|
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/Transforms/SLPVectorizer/X86/ |
H A D | bad_types.ll | 16 ; CHECK-NEXT: [[B_AND:%.*]] = and i64 [[B_CAST]], 42 19 ; CHECK-NEXT: store i64 [[B_AND]], i64* [[GEP]] 44 ; CHECK-NEXT: [[B_AND:%.*]] = and i64 [[B_CAST]], 42 48 ; CHECK-NEXT: [[B_PHI:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[B_AND]], [[IF_THEN]] ]
|
/dports/devel/llvm11/llvm-11.0.1.src/test/Transforms/SLPVectorizer/X86/ |
H A D | bad_types.ll | 16 ; CHECK-NEXT: [[B_AND:%.*]] = and i64 [[B_CAST]], 42 19 ; CHECK-NEXT: store i64 [[B_AND]], i64* [[GEP]] 44 ; CHECK-NEXT: [[B_AND:%.*]] = and i64 [[B_CAST]], 42 48 ; CHECK-NEXT: [[B_PHI:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[B_AND]], [[IF_THEN]] ]
|
/dports/devel/llvm10/llvm-10.0.1.src/test/Transforms/SLPVectorizer/X86/ |
H A D | bad_types.ll | 16 ; CHECK-NEXT: [[B_AND:%.*]] = and i64 [[B_CAST]], 42 19 ; CHECK-NEXT: store i64 [[B_AND]], i64* [[GEP]] 44 ; CHECK-NEXT: [[B_AND:%.*]] = and i64 [[B_CAST]], 42 48 ; CHECK-NEXT: [[B_PHI:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[B_AND]], [[IF_THEN]] ]
|
/dports/devel/llvm90/llvm-9.0.1.src/test/Transforms/SLPVectorizer/X86/ |
H A D | bad_types.ll | 16 ; CHECK-NEXT: [[B_AND:%.*]] = and i64 [[B_CAST]], 42 19 ; CHECK-NEXT: store i64 [[B_AND]], i64* [[GEP]] 44 ; CHECK-NEXT: [[B_AND:%.*]] = and i64 [[B_CAST]], 42 48 ; CHECK-NEXT: [[B_PHI:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[B_AND]], [[IF_THEN]] ]
|
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/Transforms/SLPVectorizer/X86/ |
H A D | bad_types.ll | 16 ; CHECK-NEXT: [[B_AND:%.*]] = and i64 [[B_CAST]], 42 19 ; CHECK-NEXT: store i64 [[B_AND]], i64* [[GEP]] 44 ; CHECK-NEXT: [[B_AND:%.*]] = and i64 [[B_CAST]], 42 48 ; CHECK-NEXT: [[B_PHI:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[B_AND]], [[IF_THEN]] ]
|
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/Transforms/SLPVectorizer/X86/ |
H A D | bad_types.ll | 16 ; CHECK-NEXT: [[B_AND:%.*]] = and i64 [[B_CAST]], 42 19 ; CHECK-NEXT: store i64 [[B_AND]], i64* [[GEP]] 44 ; CHECK-NEXT: [[B_AND:%.*]] = and i64 [[B_CAST]], 42 48 ; CHECK-NEXT: [[B_PHI:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[B_AND]], [[IF_THEN]] ]
|
/dports/devel/llvm80/llvm-8.0.1.src/test/Transforms/SLPVectorizer/X86/ |
H A D | bad_types.ll | 16 ; CHECK-NEXT: [[B_AND:%.*]] = and i64 [[B_CAST]], 42 19 ; CHECK-NEXT: store i64 [[B_AND]], i64* [[GEP]] 44 ; CHECK-NEXT: [[B_AND:%.*]] = and i64 [[B_CAST]], 42 48 ; CHECK-NEXT: [[B_PHI:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[B_AND]], [[IF_THEN]] ]
|
/dports/www/tikiwiki/tiki-21.2/vendor_bundled/vendor/zendframework/zendsearch/library/ZendSearch/Lucene/Search/ |
H A D | BooleanExpressionRecognizer.php | 202 if (QueryParser::getDefaultOperator() == QueryParser::B_AND) { 217 if (QueryParser::getDefaultOperator() == QueryParser::B_AND) {
|
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/Transforms/SLPVectorizer/X86/ |
H A D | bad_types.ll | 16 ; CHECK-NEXT: [[B_AND:%.*]] = and i64 [[B_CAST]], 42 19 ; CHECK-NEXT: store i64 [[B_AND]], i64* [[GEP]], align 8 44 ; CHECK-NEXT: [[B_AND:%.*]] = and i64 [[B_CAST]], 42 48 ; CHECK-NEXT: [[B_PHI:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[B_AND]], [[IF_THEN]] ]
|
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/Transforms/SLPVectorizer/X86/ |
H A D | bad_types.ll | 16 ; CHECK-NEXT: [[B_AND:%.*]] = and i64 [[B_CAST]], 42 19 ; CHECK-NEXT: store i64 [[B_AND]], i64* [[GEP]], align 8 44 ; CHECK-NEXT: [[B_AND:%.*]] = and i64 [[B_CAST]], 42 48 ; CHECK-NEXT: [[B_PHI:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[B_AND]], [[IF_THEN]] ]
|