1 ///////////////////////////////////////////////////////////////////////// 2 // $Id: decoder.h 13963 2020-10-03 09:23:28Z sshwarts $ 3 ///////////////////////////////////////////////////////////////////////// 4 // 5 // Copyright (C) 2016-2020 The Bochs Project 6 // 7 // This library is free software; you can redistribute it and/or 8 // modify it under the terms of the GNU Lesser General Public 9 // License as published by the Free Software Foundation; either 10 // version 2 of the License, or (at your option) any later version. 11 // 12 // This library is distributed in the hope that it will be useful, 13 // but WITHOUT ANY WARRANTY; without even the implied warranty of 14 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 // Lesser General Public License for more details. 16 // 17 // You should have received a copy of the GNU Lesser General Public 18 // License along with this library; if not, write to the Free Software 19 // Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA 20 ///////////////////////////////////////////////////////////////////////// 21 22 #ifndef BX_X86_DECODER_H 23 #define BX_X86_DECODER_H 24 25 // x86 Arch features 26 enum x86_feature_name { 27 BX_ISA_386 = 0, /* 386 or earlier instruction */ 28 BX_ISA_X87, /* FPU (X87) instruction */ 29 BX_ISA_486, /* 486 new instruction */ 30 BX_ISA_PENTIUM, /* Pentium new instruction */ 31 BX_ISA_P6, /* P6 new instruction */ 32 BX_ISA_MMX, /* MMX instruction */ 33 BX_ISA_3DNOW, /* 3DNow! instruction (AMD) */ 34 BX_ISA_DEBUG_EXTENSIONS, /* Debug Extensions support */ 35 BX_ISA_VME, /* VME support */ 36 BX_ISA_PSE, /* PSE support */ 37 BX_ISA_PAE, /* PAE support */ 38 BX_ISA_PGE, /* Global Pages support */ 39 BX_ISA_PSE36, /* PSE-36 support */ 40 BX_ISA_MTRR, /* MTRR support */ 41 BX_ISA_PAT, /* PAT support */ 42 BX_ISA_SYSCALL_SYSRET_LEGACY, /* SYSCALL/SYSRET in legacy mode (AMD) */ 43 BX_ISA_SYSENTER_SYSEXIT, /* SYSENTER/SYSEXIT instruction */ 44 BX_ISA_CLFLUSH, /* CLFLUSH instruction */ 45 BX_ISA_CLFLUSHOPT, /* CLFLUSHOPT instruction */ 46 BX_ISA_CLWB, /* CLWB instruction */ 47 BX_ISA_CLDEMOTE, /* CLDEMOTE instruction */ 48 BX_ISA_SSE, /* SSE instruction */ 49 BX_ISA_SSE2, /* SSE2 instruction */ 50 BX_ISA_SSE3, /* SSE3 instruction */ 51 BX_ISA_SSSE3, /* SSSE3 instruction */ 52 BX_ISA_SSE4_1, /* SSE4_1 instruction */ 53 BX_ISA_SSE4_2, /* SSE4_2 instruction */ 54 BX_ISA_POPCNT, /* POPCNT instruction */ 55 BX_ISA_MONITOR_MWAIT, /* MONITOR/MWAIT instruction */ 56 BX_ISA_MONITORX_MWAITX, /* MONITORX/MWAITX instruction (AMD) */ 57 BX_ISA_WAITPKG, /* TPAUSE/UMONITOR/UMWAIT instructions */ 58 BX_ISA_VMX, /* VMX instruction */ 59 BX_ISA_SMX, /* SMX instruction */ 60 BX_ISA_LONG_MODE, /* Long Mode (x86-64) support */ 61 BX_ISA_LM_LAHF_SAHF, /* Long Mode LAHF/SAHF instruction */ 62 BX_ISA_NX, /* No-Execute support */ 63 BX_ISA_1G_PAGES, /* 1Gb pages support */ 64 BX_ISA_CMPXCHG16B, /* CMPXCHG16B instruction */ 65 BX_ISA_RDTSCP, /* RDTSCP instruction */ 66 BX_ISA_FFXSR, /* EFER.FFXSR support */ 67 BX_ISA_XSAVE, /* XSAVE/XRSTOR extensions instruction */ 68 BX_ISA_XSAVEOPT, /* XSAVEOPT instruction */ 69 BX_ISA_XSAVEC, /* XSAVEC instruction */ 70 BX_ISA_XSAVES, /* XSAVES instruction */ 71 BX_ISA_AES_PCLMULQDQ, /* AES+PCLMULQDQ instructions */ 72 BX_ISA_VAES_VPCLMULQDQ, /* Wide vector versions of AES+PCLMULQDQ instructions */ 73 BX_ISA_MOVBE, /* MOVBE instruction */ 74 BX_ISA_FSGSBASE, /* FS/GS BASE access instruction */ 75 BX_ISA_INVPCID, /* INVPCID instruction */ 76 BX_ISA_AVX, /* AVX instruction */ 77 BX_ISA_AVX2, /* AVX2 instruction */ 78 BX_ISA_AVX_F16C, /* AVX F16 convert instruction */ 79 BX_ISA_AVX_FMA, /* AVX FMA instruction */ 80 BX_ISA_ALT_MOV_CR8, /* LOCK CR0 access CR8 (AMD) */ 81 BX_ISA_SSE4A, /* SSE4A instruction (AMD) */ 82 BX_ISA_MISALIGNED_SSE, /* Misaligned SSE (AMD) */ 83 BX_ISA_LZCNT, /* LZCNT instruction */ 84 BX_ISA_BMI1, /* BMI1 instruction */ 85 BX_ISA_BMI2, /* BMI2 instruction */ 86 BX_ISA_FMA4, /* FMA4 instruction (AMD) */ 87 BX_ISA_XOP, /* XOP instruction (AMD) */ 88 BX_ISA_TBM, /* TBM instruction (AMD) */ 89 BX_ISA_SVM, /* SVM instruction (AMD) */ 90 BX_ISA_RDRAND, /* RDRAND instruction */ 91 BX_ISA_ADX, /* ADCX/ADOX instruction */ 92 BX_ISA_SMAP, /* SMAP support */ 93 BX_ISA_RDSEED, /* RDSEED instruction */ 94 BX_ISA_SHA, /* SHA instruction */ 95 BX_ISA_GFNI, /* GFNI instruction */ 96 BX_ISA_AVX512, /* AVX-512 instruction */ 97 BX_ISA_AVX512_CD, /* AVX-512 Conflict Detection instruction */ 98 BX_ISA_AVX512_PF, /* AVX-512 Sparse Prefetch instruction */ 99 BX_ISA_AVX512_ER, /* AVX-512 Exponential/Reciprocal instruction */ 100 BX_ISA_AVX512_DQ, /* AVX-512DQ instruction */ 101 BX_ISA_AVX512_BW, /* AVX-512 Byte/Word instruction */ 102 BX_ISA_AVX512_VL, /* AVX-512 Vector Length extensions */ 103 BX_ISA_AVX512_VBMI, /* AVX-512 VBMI : Vector Bit Manipulation Instructions */ 104 BX_ISA_AVX512_VBMI2, /* AVX-512 VBMI2 : Vector Bit Manipulation Instructions */ 105 BX_ISA_AVX512_IFMA52, /* AVX-512 IFMA52 Instructions */ 106 BX_ISA_AVX512_VPOPCNTDQ, /* AVX-512 VPOPCNTD/VPOPCNTQ Instructions */ 107 BX_ISA_AVX512_VNNI, /* AVX-512 VNNI Instructions */ 108 BX_ISA_AVX512_BITALG, /* AVX-512 BITALG Instructions */ 109 BX_ISA_AVX512_VP2INTERSECT, /* AVX-512 VP2INTERSECT Instructions */ 110 BX_ISA_AVX_VNNI, /* AVX encoded VNNI Instructions */ 111 BX_ISA_XAPIC, /* XAPIC support */ 112 BX_ISA_X2APIC, /* X2APIC support */ 113 BX_ISA_XAPIC_EXT, /* XAPIC Extensions support */ 114 BX_ISA_PCID, /* PCID pages support */ 115 BX_ISA_SMEP, /* SMEP support */ 116 BX_ISA_TSC_ADJUST, /* TSC-Adjust MSR */ 117 BX_ISA_TSC_DEADLINE, /* TSC-Deadline */ 118 BX_ISA_FOPCODE_DEPRECATION, /* FOPCODE Deprecation - FOPCODE update on unmasked x87 exception only */ 119 BX_ISA_FCS_FDS_DEPRECATION, /* FCS/FDS Deprecation */ 120 BX_ISA_FDP_DEPRECATION, /* FDP Deprecation - FDP update on unmasked x87 exception only */ 121 BX_ISA_PKU, /* User-Mode Protection Keys */ 122 BX_ISA_PKS, /* Supervisor-Mode Protection Keys */ 123 BX_ISA_UMIP, /* User-Mode Instructions Prevention */ 124 BX_ISA_RDPID, /* RDPID Support */ 125 BX_ISA_TCE, /* Translation Cache Extensions (TCE) support (AMD) */ 126 BX_ISA_CLZERO, /* CLZERO instruction support (AMD) */ 127 BX_ISA_SCA_MITIGATIONS, /* SCA Mitigations */ 128 BX_ISA_CET, /* Control Flow Enforcement */ 129 BX_ISA_EXTENSION_LAST 130 }; 131 132 #define BX_ISA_EXTENSIONS_ARRAY_SIZE (4) 133 134 #if (BX_ISA_EXTENSION_LAST) >= (BX_ISA_EXTENSIONS_ARRAY_SIZE*32) 135 #error "ISA extensions array limit exceeded!" 136 #endif 137 138 // segment register encoding 139 enum BxSegregs { 140 BX_SEG_REG_ES = 0, 141 BX_SEG_REG_CS = 1, 142 BX_SEG_REG_SS = 2, 143 BX_SEG_REG_DS = 3, 144 BX_SEG_REG_FS = 4, 145 BX_SEG_REG_GS = 5, 146 // NULL now has to fit in 3 bits. 147 BX_SEG_REG_NULL = 7 148 }; 149 150 #define BX_NULL_SEG_REG(seg) ((seg) == BX_SEG_REG_NULL) 151 152 enum BxRegs8L { 153 BX_8BIT_REG_AL, 154 BX_8BIT_REG_CL, 155 BX_8BIT_REG_DL, 156 BX_8BIT_REG_BL, 157 BX_8BIT_REG_SPL, 158 BX_8BIT_REG_BPL, 159 BX_8BIT_REG_SIL, 160 BX_8BIT_REG_DIL, 161 #if BX_SUPPORT_X86_64 162 BX_8BIT_REG_R8, 163 BX_8BIT_REG_R9, 164 BX_8BIT_REG_R10, 165 BX_8BIT_REG_R11, 166 BX_8BIT_REG_R12, 167 BX_8BIT_REG_R13, 168 BX_8BIT_REG_R14, 169 BX_8BIT_REG_R15 170 #endif 171 }; 172 173 enum BxRegs8H { 174 BX_8BIT_REG_AH, 175 BX_8BIT_REG_CH, 176 BX_8BIT_REG_DH, 177 BX_8BIT_REG_BH 178 }; 179 180 enum BxRegs16 { 181 BX_16BIT_REG_AX, 182 BX_16BIT_REG_CX, 183 BX_16BIT_REG_DX, 184 BX_16BIT_REG_BX, 185 BX_16BIT_REG_SP, 186 BX_16BIT_REG_BP, 187 BX_16BIT_REG_SI, 188 BX_16BIT_REG_DI, 189 #if BX_SUPPORT_X86_64 190 BX_16BIT_REG_R8, 191 BX_16BIT_REG_R9, 192 BX_16BIT_REG_R10, 193 BX_16BIT_REG_R11, 194 BX_16BIT_REG_R12, 195 BX_16BIT_REG_R13, 196 BX_16BIT_REG_R14, 197 BX_16BIT_REG_R15, 198 #endif 199 }; 200 201 enum BxRegs32 { 202 BX_32BIT_REG_EAX, 203 BX_32BIT_REG_ECX, 204 BX_32BIT_REG_EDX, 205 BX_32BIT_REG_EBX, 206 BX_32BIT_REG_ESP, 207 BX_32BIT_REG_EBP, 208 BX_32BIT_REG_ESI, 209 BX_32BIT_REG_EDI, 210 #if BX_SUPPORT_X86_64 211 BX_32BIT_REG_R8, 212 BX_32BIT_REG_R9, 213 BX_32BIT_REG_R10, 214 BX_32BIT_REG_R11, 215 BX_32BIT_REG_R12, 216 BX_32BIT_REG_R13, 217 BX_32BIT_REG_R14, 218 BX_32BIT_REG_R15, 219 #endif 220 }; 221 222 #if BX_SUPPORT_X86_64 223 enum BxRegs64 { 224 BX_64BIT_REG_RAX, 225 BX_64BIT_REG_RCX, 226 BX_64BIT_REG_RDX, 227 BX_64BIT_REG_RBX, 228 BX_64BIT_REG_RSP, 229 BX_64BIT_REG_RBP, 230 BX_64BIT_REG_RSI, 231 BX_64BIT_REG_RDI, 232 BX_64BIT_REG_R8, 233 BX_64BIT_REG_R9, 234 BX_64BIT_REG_R10, 235 BX_64BIT_REG_R11, 236 BX_64BIT_REG_R12, 237 BX_64BIT_REG_R13, 238 BX_64BIT_REG_R14, 239 BX_64BIT_REG_R15, 240 }; 241 #endif 242 243 #if BX_SUPPORT_X86_64 244 # define BX_GENERAL_REGISTERS 16 245 #else 246 # define BX_GENERAL_REGISTERS 8 247 #endif 248 249 static const unsigned BX_16BIT_REG_IP = (BX_GENERAL_REGISTERS), 250 BX_32BIT_REG_EIP = (BX_GENERAL_REGISTERS), 251 BX_64BIT_REG_RIP = (BX_GENERAL_REGISTERS); 252 253 static const unsigned BX_32BIT_REG_SSP = (BX_GENERAL_REGISTERS+1), 254 BX_64BIT_REG_SSP = (BX_GENERAL_REGISTERS+1); 255 256 static const unsigned BX_TMP_REGISTER = (BX_GENERAL_REGISTERS+2); 257 static const unsigned BX_NIL_REGISTER = (BX_GENERAL_REGISTERS+3); 258 259 enum OpmaskRegs { 260 BX_REG_OPMASK_K0, 261 BX_REG_OPMASK_K1, 262 BX_REG_OPMASK_K2, 263 BX_REG_OPMASK_K3, 264 BX_REG_OPMASK_K4, 265 BX_REG_OPMASK_K5, 266 BX_REG_OPMASK_K6, 267 BX_REG_OPMASK_K7 268 }; 269 270 // AVX Registers 271 enum bx_avx_vector_length { 272 BX_NO_VL, 273 BX_VL128 = 1, 274 BX_VL256 = 2, 275 BX_VL512 = 4, 276 }; 277 278 #if BX_SUPPORT_EVEX 279 # define BX_VLMAX BX_VL512 280 #else 281 # if BX_SUPPORT_AVX 282 # define BX_VLMAX BX_VL256 283 # else 284 # define BX_VLMAX BX_VL128 285 # endif 286 #endif 287 288 #if BX_SUPPORT_EVEX 289 # define BX_XMM_REGISTERS 32 290 #else 291 # if BX_SUPPORT_X86_64 292 # define BX_XMM_REGISTERS 16 293 # else 294 # define BX_XMM_REGISTERS 8 295 # endif 296 #endif 297 298 static const unsigned BX_VECTOR_TMP_REGISTER = (BX_XMM_REGISTERS); 299 300 #endif // BX_X86_DECODER_H 301 302