/dports/lang/gcc48/gcc-4.8.5/libitm/config/x86/ |
H A D | cacheline.h | 32 # define CACHELINE_SIZE 64 macro 34 # define CACHELINE_SIZE 32 macro 46 unsigned char b[CACHELINE_SIZE] __attribute__((aligned(CACHELINE_SIZE))); 49 uint16_t u16[CACHELINE_SIZE / sizeof(uint16_t)]; 50 uint32_t u32[CACHELINE_SIZE / sizeof(uint32_t)]; 51 uint64_t u64[CACHELINE_SIZE / sizeof(uint64_t)]; 52 gtm_word w[CACHELINE_SIZE / sizeof(gtm_word)]; 55 __m64 m64[CACHELINE_SIZE / sizeof(__m64)]; 58 __m128 m128[CACHELINE_SIZE / sizeof(__m128)]; 64 __m256 m256[CACHELINE_SIZE / sizeof(__m256)]; [all …]
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/dports/devel/arm-none-eabi-gcc492/gcc-4.9.2/libitm/config/x86/ |
H A D | cacheline.h | 32 # define CACHELINE_SIZE 64 macro 34 # define CACHELINE_SIZE 32 macro 46 unsigned char b[CACHELINE_SIZE] __attribute__((aligned(CACHELINE_SIZE))); 49 uint16_t u16[CACHELINE_SIZE / sizeof(uint16_t)]; 50 uint32_t u32[CACHELINE_SIZE / sizeof(uint32_t)]; 51 uint64_t u64[CACHELINE_SIZE / sizeof(uint64_t)]; 52 gtm_word w[CACHELINE_SIZE / sizeof(gtm_word)]; 55 __m64 m64[CACHELINE_SIZE / sizeof(__m64)]; 58 __m128 m128[CACHELINE_SIZE / sizeof(__m128)]; 64 __m256 m256[CACHELINE_SIZE / sizeof(__m256)]; [all …]
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/dports/devel/mingw32-gcc/gcc-4.8.1/libitm/config/x86/ |
H A D | cacheline.h | 32 # define CACHELINE_SIZE 64 macro 34 # define CACHELINE_SIZE 32 macro 46 unsigned char b[CACHELINE_SIZE] __attribute__((aligned(CACHELINE_SIZE))); 49 uint16_t u16[CACHELINE_SIZE / sizeof(uint16_t)]; 50 uint32_t u32[CACHELINE_SIZE / sizeof(uint32_t)]; 51 uint64_t u64[CACHELINE_SIZE / sizeof(uint64_t)]; 52 gtm_word w[CACHELINE_SIZE / sizeof(gtm_word)]; 55 __m64 m64[CACHELINE_SIZE / sizeof(__m64)]; 58 __m128 m128[CACHELINE_SIZE / sizeof(__m128)]; 64 __m256 m256[CACHELINE_SIZE / sizeof(__m256)]; [all …]
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/dports/devel/arm-none-eabi-gcc492/gcc-4.9.2/libitm/config/generic/ |
H A D | cacheline.h | 36 #ifndef CACHELINE_SIZE 37 # define CACHELINE_SIZE 32 macro 42 typedef sized_integral<CACHELINE_SIZE / 8>::type gtm_cacheline_mask; 47 unsigned char b[CACHELINE_SIZE] __attribute__((aligned(CACHELINE_SIZE))); 50 uint16_t u16[CACHELINE_SIZE / sizeof(uint16_t)]; 51 uint32_t u32[CACHELINE_SIZE / sizeof(uint32_t)]; 52 uint64_t u64[CACHELINE_SIZE / sizeof(uint64_t)]; 53 gtm_word w[CACHELINE_SIZE / sizeof(gtm_word)];
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/dports/devel/mingw32-gcc/gcc-4.8.1/libitm/config/generic/ |
H A D | cacheline.h | 36 #ifndef CACHELINE_SIZE 37 # define CACHELINE_SIZE 32 macro 42 typedef sized_integral<CACHELINE_SIZE / 8>::type gtm_cacheline_mask; 47 unsigned char b[CACHELINE_SIZE] __attribute__((aligned(CACHELINE_SIZE))); 50 uint16_t u16[CACHELINE_SIZE / sizeof(uint16_t)]; 51 uint32_t u32[CACHELINE_SIZE / sizeof(uint32_t)]; 52 uint64_t u64[CACHELINE_SIZE / sizeof(uint64_t)]; 53 gtm_word w[CACHELINE_SIZE / sizeof(gtm_word)];
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/dports/lang/gcc48/gcc-4.8.5/libitm/config/generic/ |
H A D | cacheline.h | 36 #ifndef CACHELINE_SIZE 37 # define CACHELINE_SIZE 32 macro 42 typedef sized_integral<CACHELINE_SIZE / 8>::type gtm_cacheline_mask; 47 unsigned char b[CACHELINE_SIZE] __attribute__((aligned(CACHELINE_SIZE))); 50 uint16_t u16[CACHELINE_SIZE / sizeof(uint16_t)]; 51 uint32_t u32[CACHELINE_SIZE / sizeof(uint32_t)]; 52 uint64_t u64[CACHELINE_SIZE / sizeof(uint64_t)]; 53 gtm_word w[CACHELINE_SIZE / sizeof(gtm_word)];
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/dports/net-mgmt/aircrack-ng/aircrack-ng-1.5.2/src/aircrack-crypto/ |
H A D | crypto_engine.h | 103 #ifndef CACHELINE_SIZE 120 CACHELINE_SIZE); 127 CACHELINE_SIZE); 134 CACHELINE_SIZE / 2); 141 CACHELINE_SIZE / 2); 148 CACHELINE_SIZE * 2); 154 CACHELINE_SIZE); 159 % CACHELINE_SIZE) 162 % CACHELINE_SIZE) 168 % CACHELINE_SIZE) [all …]
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/dports/devel/grpc/grpc-1.42.0/test/cpp/microbenchmarks/ |
H A D | bm_threadpool.cc | 244 #define CACHELINE_SIZE 64 macro 246 #define CACHELINE_SIZE 128 macro 248 #define CACHELINE_SIZE 64 macro 251 #define CACHELINE_SIZE 32 macro 253 #define CACHELINE_SIZE 64 macro 256 #ifndef CACHELINE_SIZE 257 #define CACHELINE_SIZE 64 macro 285 char pad[CACHELINE_SIZE];
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/dports/devel/grpc130/grpc-1.30.2/test/cpp/microbenchmarks/ |
H A D | bm_threadpool.cc | 241 #define CACHELINE_SIZE 64 macro 243 #define CACHELINE_SIZE 128 macro 245 #define CACHELINE_SIZE 64 macro 248 #define CACHELINE_SIZE 32 macro 250 #define CACHELINE_SIZE 64 macro 253 #ifndef CACHELINE_SIZE 254 #define CACHELINE_SIZE 64 macro 283 char pad[CACHELINE_SIZE];
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/dports/devel/grpc134/grpc-1.34.1/test/cpp/microbenchmarks/ |
H A D | bm_threadpool.cc | 242 #define CACHELINE_SIZE 64 macro 244 #define CACHELINE_SIZE 128 macro 246 #define CACHELINE_SIZE 64 macro 249 #define CACHELINE_SIZE 32 macro 251 #define CACHELINE_SIZE 64 macro 254 #ifndef CACHELINE_SIZE 255 #define CACHELINE_SIZE 64 macro 284 char pad[CACHELINE_SIZE];
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/dports/lang/gcc48/gcc-4.8.5/libitm/config/sparc/ |
H A D | cacheline.h | 34 # define CACHELINE_SIZE 64 macro 36 # define CACHELINE_SIZE 32 macro
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/dports/devel/arm-none-eabi-gcc492/gcc-4.9.2/libitm/config/sparc/ |
H A D | cacheline.h | 34 # define CACHELINE_SIZE 64 macro 36 # define CACHELINE_SIZE 32 macro
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/dports/devel/mingw32-gcc/gcc-4.8.1/libitm/config/sparc/ |
H A D | cacheline.h | 34 # define CACHELINE_SIZE 64 macro 36 # define CACHELINE_SIZE 32 macro
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/dports/devel/arm-none-eabi-gcc492/gcc-4.9.2/libitm/config/powerpc/ |
H A D | cacheline.h | 35 # define CACHELINE_SIZE 64 macro 37 # define CACHELINE_SIZE 32 macro
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/dports/devel/mingw32-gcc/gcc-4.8.1/libitm/config/powerpc/ |
H A D | cacheline.h | 35 # define CACHELINE_SIZE 64 macro 37 # define CACHELINE_SIZE 32 macro
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/dports/lang/gcc48/gcc-4.8.5/libitm/config/powerpc/ |
H A D | cacheline.h | 35 # define CACHELINE_SIZE 64 macro 37 # define CACHELINE_SIZE 32 macro
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/dports/devel/ga/ga-5.8/comex/src-ofi/ |
H A D | env.h | 8 #define CACHELINE_SIZE 64 macro 20 } env_data_t __attribute__ ((aligned (CACHELINE_SIZE)));
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/dports/net/kamailio/kamailio-5.4.5/src/modules/auth/ |
H A D | nid.h | 54 #define CACHELINE_SIZE 256 /* more then most real-word cachelines */ macro 62 char pad[CACHELINE_SIZE-sizeof(atomic_t)];/* padding to cacheline size */
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/dports/lang/clover/mesa-21.3.6/src/intel/common/ |
H A D | intel_clflush.h | 27 #define CACHELINE_SIZE 64 macro 38 p += CACHELINE_SIZE; in intel_clflush_range()
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/dports/graphics/libosmesa-gallium/mesa-21.3.6/src/intel/common/ |
H A D | intel_clflush.h | 27 #define CACHELINE_SIZE 64 macro 38 p += CACHELINE_SIZE; in intel_clflush_range()
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/dports/graphics/libosmesa/mesa-21.3.6/src/intel/common/ |
H A D | intel_clflush.h | 27 #define CACHELINE_SIZE 64 macro 38 p += CACHELINE_SIZE; in intel_clflush_range()
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/dports/graphics/mesa-gallium-xa/mesa-21.3.6/src/intel/common/ |
H A D | intel_clflush.h | 27 #define CACHELINE_SIZE 64 macro 38 p += CACHELINE_SIZE; in intel_clflush_range()
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/dports/graphics/mesa-libs/mesa-21.3.6/src/intel/common/ |
H A D | intel_clflush.h | 27 #define CACHELINE_SIZE 64 macro 38 p += CACHELINE_SIZE; in intel_clflush_range()
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/dports/graphics/mesa-dri-gallium/mesa-21.3.6/src/intel/common/ |
H A D | intel_clflush.h | 27 #define CACHELINE_SIZE 64 macro 38 p += CACHELINE_SIZE; in intel_clflush_range()
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/dports/graphics/mesa-gallium-va/mesa-21.3.6/src/intel/common/ |
H A D | intel_clflush.h | 27 #define CACHELINE_SIZE 64 macro 38 p += CACHELINE_SIZE; in intel_clflush_range()
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