/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/arm/mach-sunxi/ |
H A D | dram_sun4i.c | 259 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(15)); in mctl_setup_dram_clock() 264 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(16)); in mctl_setup_dram_clock() 269 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(31)); in mctl_setup_dram_clock() 274 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(13)); in mctl_setup_dram_clock() 279 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11)); in mctl_setup_dram_clock() 284 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(clk / 24)); in mctl_setup_dram_clock()
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/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/arm/mach-sunxi/ |
H A D | dram_sun4i.c | 259 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(15)); in mctl_setup_dram_clock() 264 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(16)); in mctl_setup_dram_clock() 269 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(31)); in mctl_setup_dram_clock() 274 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(13)); in mctl_setup_dram_clock() 279 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11)); in mctl_setup_dram_clock() 284 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(clk / 24)); in mctl_setup_dram_clock()
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/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/mach-sunxi/ |
H A D | dram_sun4i.c | 261 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(15)); in mctl_setup_dram_clock() 266 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(16)); in mctl_setup_dram_clock() 271 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(31)); in mctl_setup_dram_clock() 276 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(13)); in mctl_setup_dram_clock() 281 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11)); in mctl_setup_dram_clock() 286 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(clk / 24)); in mctl_setup_dram_clock()
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/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/arm/mach-sunxi/ |
H A D | dram_sun4i.c | 261 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(15)); in mctl_setup_dram_clock() 266 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(16)); in mctl_setup_dram_clock() 271 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(31)); in mctl_setup_dram_clock() 276 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(13)); in mctl_setup_dram_clock() 281 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11)); in mctl_setup_dram_clock() 286 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(clk / 24)); in mctl_setup_dram_clock()
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/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/mach-sunxi/ |
H A D | dram_sun4i.c | 261 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(15)); in mctl_setup_dram_clock() 266 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(16)); in mctl_setup_dram_clock() 271 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(31)); in mctl_setup_dram_clock() 276 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(13)); in mctl_setup_dram_clock() 281 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11)); in mctl_setup_dram_clock() 286 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(clk / 24)); in mctl_setup_dram_clock()
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/dports/sysutils/u-boot-chip/u-boot-2021.07/arch/arm/mach-sunxi/ |
H A D | dram_sun4i.c | 261 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(15)); in mctl_setup_dram_clock() 266 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(16)); in mctl_setup_dram_clock() 271 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(31)); in mctl_setup_dram_clock() 276 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(13)); in mctl_setup_dram_clock() 281 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11)); in mctl_setup_dram_clock() 286 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(clk / 24)); in mctl_setup_dram_clock()
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/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/mach-sunxi/ |
H A D | dram_sun4i.c | 261 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(15)); in mctl_setup_dram_clock() 266 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(16)); in mctl_setup_dram_clock() 271 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(31)); in mctl_setup_dram_clock() 276 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(13)); in mctl_setup_dram_clock() 281 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11)); in mctl_setup_dram_clock() 286 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(clk / 24)); in mctl_setup_dram_clock()
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/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/arch/arm/mach-sunxi/ |
H A D | dram_sun4i.c | 261 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(15)); in mctl_setup_dram_clock() 266 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(16)); in mctl_setup_dram_clock() 271 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(31)); in mctl_setup_dram_clock() 276 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(13)); in mctl_setup_dram_clock() 281 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11)); in mctl_setup_dram_clock() 286 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(clk / 24)); in mctl_setup_dram_clock()
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/dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/arm/mach-sunxi/ |
H A D | dram_sun4i.c | 261 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(15)); in mctl_setup_dram_clock() 266 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(16)); in mctl_setup_dram_clock() 271 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(31)); in mctl_setup_dram_clock() 276 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(13)); in mctl_setup_dram_clock() 281 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11)); in mctl_setup_dram_clock() 286 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(clk / 24)); in mctl_setup_dram_clock()
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/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/arm/mach-sunxi/ |
H A D | dram_sun4i.c | 261 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(15)); in mctl_setup_dram_clock() 266 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(16)); in mctl_setup_dram_clock() 271 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(31)); in mctl_setup_dram_clock() 276 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(13)); in mctl_setup_dram_clock() 281 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11)); in mctl_setup_dram_clock() 286 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(clk / 24)); in mctl_setup_dram_clock()
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/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/mach-sunxi/ |
H A D | dram_sun4i.c | 261 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(15)); in mctl_setup_dram_clock() 266 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(16)); in mctl_setup_dram_clock() 271 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(31)); in mctl_setup_dram_clock() 276 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(13)); in mctl_setup_dram_clock() 281 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11)); in mctl_setup_dram_clock() 286 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(clk / 24)); in mctl_setup_dram_clock()
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/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/arm/mach-sunxi/ |
H A D | dram_sun4i.c | 261 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(15)); in mctl_setup_dram_clock() 266 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(16)); in mctl_setup_dram_clock() 271 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(31)); in mctl_setup_dram_clock() 276 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(13)); in mctl_setup_dram_clock() 281 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11)); in mctl_setup_dram_clock() 286 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(clk / 24)); in mctl_setup_dram_clock()
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/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/arm/mach-sunxi/ |
H A D | dram_sun4i.c | 261 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(15)); in mctl_setup_dram_clock() 266 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(16)); in mctl_setup_dram_clock() 271 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(31)); in mctl_setup_dram_clock() 276 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(13)); in mctl_setup_dram_clock() 281 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11)); in mctl_setup_dram_clock() 286 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(clk / 24)); in mctl_setup_dram_clock()
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/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/mach-sunxi/ |
H A D | dram_sun4i.c | 261 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(15)); in mctl_setup_dram_clock() 266 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(16)); in mctl_setup_dram_clock() 271 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(31)); in mctl_setup_dram_clock() 276 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(13)); in mctl_setup_dram_clock() 281 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11)); in mctl_setup_dram_clock() 286 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(clk / 24)); in mctl_setup_dram_clock()
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/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/arm/mach-sunxi/ |
H A D | dram_sun4i.c | 261 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(15)); in mctl_setup_dram_clock() 266 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(16)); in mctl_setup_dram_clock() 271 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(31)); in mctl_setup_dram_clock() 276 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(13)); in mctl_setup_dram_clock() 281 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11)); in mctl_setup_dram_clock() 286 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(clk / 24)); in mctl_setup_dram_clock()
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/dports/sysutils/u-boot-nanopi-a64/u-boot-2021.07/arch/arm/mach-sunxi/ |
H A D | dram_sun4i.c | 261 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(15)); in mctl_setup_dram_clock() 266 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(16)); in mctl_setup_dram_clock() 271 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(31)); in mctl_setup_dram_clock() 276 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(13)); in mctl_setup_dram_clock() 281 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11)); in mctl_setup_dram_clock() 286 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(clk / 24)); in mctl_setup_dram_clock()
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/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/arch/arm/mach-sunxi/ |
H A D | dram_sun4i.c | 261 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(15)); in mctl_setup_dram_clock() 266 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(16)); in mctl_setup_dram_clock() 271 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(31)); in mctl_setup_dram_clock() 276 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(13)); in mctl_setup_dram_clock() 281 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11)); in mctl_setup_dram_clock() 286 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(clk / 24)); in mctl_setup_dram_clock()
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/dports/sysutils/u-boot-bananapi/u-boot-2021.07/arch/arm/mach-sunxi/ |
H A D | dram_sun4i.c | 261 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(15)); in mctl_setup_dram_clock() 266 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(16)); in mctl_setup_dram_clock() 271 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(31)); in mctl_setup_dram_clock() 276 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(13)); in mctl_setup_dram_clock() 281 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11)); in mctl_setup_dram_clock() 286 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(clk / 24)); in mctl_setup_dram_clock()
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/dports/sysutils/u-boot-wandboard/u-boot-2021.07/arch/arm/mach-sunxi/ |
H A D | dram_sun4i.c | 261 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(15)); in mctl_setup_dram_clock() 266 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(16)); in mctl_setup_dram_clock() 271 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(31)); in mctl_setup_dram_clock() 276 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(13)); in mctl_setup_dram_clock() 281 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11)); in mctl_setup_dram_clock() 286 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(clk / 24)); in mctl_setup_dram_clock()
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/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/arm/mach-sunxi/ |
H A D | dram_sun4i.c | 259 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(15)); in mctl_setup_dram_clock() 264 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(16)); in mctl_setup_dram_clock() 269 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(31)); in mctl_setup_dram_clock() 274 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(13)); in mctl_setup_dram_clock() 279 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11)); in mctl_setup_dram_clock() 284 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(clk / 24)); in mctl_setup_dram_clock()
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/arm/mach-sunxi/ |
H A D | dram_sun4i.c | 259 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(15)); 264 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(16)); 269 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(31)); 274 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(13)); 279 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11)); 284 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(clk / 24));
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/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/arm/mach-sunxi/ |
H A D | dram_sun4i.c | 261 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(15)); in mctl_setup_dram_clock() 266 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(16)); in mctl_setup_dram_clock() 271 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(31)); in mctl_setup_dram_clock() 276 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(13)); in mctl_setup_dram_clock() 281 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11)); in mctl_setup_dram_clock() 286 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(clk / 24)); in mctl_setup_dram_clock()
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/dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/arm/mach-sunxi/ |
H A D | dram_sun4i.c | 261 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(15)); in mctl_setup_dram_clock() 266 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(16)); in mctl_setup_dram_clock() 271 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(31)); in mctl_setup_dram_clock() 276 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(13)); in mctl_setup_dram_clock() 281 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11)); in mctl_setup_dram_clock() 286 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(clk / 24)); in mctl_setup_dram_clock()
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/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/arm/mach-sunxi/ |
H A D | dram_sun4i.c | 261 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(15)); in mctl_setup_dram_clock() 266 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(16)); in mctl_setup_dram_clock() 271 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(31)); in mctl_setup_dram_clock() 276 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(13)); in mctl_setup_dram_clock() 281 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11)); in mctl_setup_dram_clock() 286 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(clk / 24)); in mctl_setup_dram_clock()
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/dports/sysutils/u-boot-pandaboard/u-boot-2021.07/arch/arm/mach-sunxi/ |
H A D | dram_sun4i.c | 261 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(15)); in mctl_setup_dram_clock() 266 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(16)); in mctl_setup_dram_clock() 271 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(31)); in mctl_setup_dram_clock() 276 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(13)); in mctl_setup_dram_clock() 281 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11)); in mctl_setup_dram_clock() 286 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(clk / 24)); in mctl_setup_dram_clock()
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