| /dports/devel/trellis/prjtrellis-5eb0ad87/database/ECP5/tiledata/MIB2_DSP2/ |
| H A D | bits.db | 67 CLK0 F58B1 F59B1
74 CLK0 F34B1 F35B1
87 CLK0 F42B1 F43B1
100 CLK0 F78B1 F79B1
107 CLK0 F74B1 F75B1
114 CLK0 F78B1 F79B1
121 CLK0 F74B1 F75B1
166 CLK0 F16B1 F17B1
179 CLK0 F20B1 F21B1
230 CLK0 F102B1 F103B1
[all …]
|
| /dports/devel/trellis/prjtrellis-5eb0ad87/database/ECP5/tiledata/MIB2_DSP7/ |
| H A D | bits.db | 67 CLK0 F4B1 F5B1 F49B1 F57B1
74 CLK0 F80B1 F81B1
93 CLK0 F24B1 F25B1
106 CLK0 F16B1 F17B1
119 CLK0 F24B1 F25B1
126 CLK0 F16B1 F17B1
133 CLK0 F58B1 F59B1
140 CLK0 F4B1 F5B1 F49B1 F57B1
192 CLK0 F38B1 F40B1 F84B1 F85B1 F94B1 F95B1
205 CLK0 F80B1 F81B1
[all …]
|
| /dports/devel/trellis/prjtrellis-5eb0ad87/database/ECP5/tiledata/MIB2_DSP4/ |
| H A D | bits.db | 121 CLK0 F12B1 F13B1
140 CLK0 F38B1 F39B1
147 CLK0 F10B1 F11B1
170 CLK0 F95B1 F96B1
177 CLK0 F60B1 F61B1
184 CLK0 F92B1 F94B1
191 CLK0 F95B1 F96B1
214 CLK0 F12B1 F13B1
238 CLK0 -
253 CLK0 -
[all …]
|
| /dports/devel/trellis/prjtrellis-5eb0ad87/database/ECP5/tiledata/MIB2_DSP0/ |
| H A D | bits.db | 195 CLK0 F36B1 F37B1
202 CLK0 F21B1 F22B1
209 CLK0 -
228 CLK0 -
235 CLK0 -
242 CLK0 F34B1 F35B1
249 CLK0 F36B1 F37B1
260 CLK0 -
287 CLK0 F21B1 F22B1
294 CLK0 F34B1 F35B1 F36B1 F37B1
[all …]
|
| /dports/devel/trellis/prjtrellis-5eb0ad87/database/ECP5/tiledata/MIB2_DSP6/ |
| H A D | bits.db | 314 CLK0 F40B1 F42B1 F46B1 F47B1
321 CLK0 F48B1 F49B1
328 CLK0 F94B1 F95B1
335 CLK0 F96B1 F97B1
342 CLK0 F62B1 F63B1 F102B1 F103B1
355 CLK0 F64B1 F65B1
380 CLK0 F24B1 F25B1 F34B1 F35B1 F72B1 F73B1
406 CLK0 F40B1 F42B1 F46B1 F47B1
413 CLK0 F62B1 F63B1 F64B1 F65B1
463 CLK0 F48B1 F49B1
[all …]
|
| /dports/devel/trellis/prjtrellis-5eb0ad87/database/ECP5/tiledata/MIB2_DSP1/ |
| H A D | bits.db | 187 CLK0 F92B1 F93B1 F96B1 F97B1
194 CLK0 F98B1 F101B1
209 CLK0 F76B1 F77B1 F88B1 F89B1
222 CLK0 F84B1 F85B1 F90B1 F91B1
235 CLK0 F92B1 F93B1 F96B1 F97B1
242 CLK0 F104B1 F105B1
275 CLK0 F98B1 F101B1
|
| /dports/security/john/john-1.9.0-jumbo-1/src/ztex/fpga-sha256crypt/ztex_inouttraffic/ |
| H A D | cmt2.v | 26 output CLK0, port
111 .CLK0 (dcm0_clk0),
126 assign CLK0 = dcm0_clk0;
|
| H A D | clocks.v | 99 .CLK0(IFCLK),
|
| /dports/security/john/john-1.9.0-jumbo-1/src/ztex/fpga-sha512crypt/ztex_inouttraffic/ |
| H A D | cmt2.v | 26 output CLK0, port
111 .CLK0 (dcm0_clk0),
126 assign CLK0 = dcm0_clk0;
|
| H A D | clocks.v | 99 .CLK0(IFCLK),
|
| /dports/security/john/john-1.9.0-jumbo-1/src/ztex/fpga-md5crypt/ztex_inouttraffic/ |
| H A D | cmt2.v | 26 output CLK0, port
111 .CLK0 (dcm0_clk0),
126 assign CLK0 = dcm0_clk0;
|
| H A D | clocks.v | 99 .CLK0(IFCLK),
|
| /dports/devel/trellis/prjtrellis-5eb0ad87/database/ECP5/tiledata/MIB2_DSP3/ |
| H A D | bits.db | 414 CLK0 F3B1 F4B1
421 CLK0 F30B1 F31B1
440 CLK0 F5B1 F6B1
447 CLK0 F3B1 F4B1
474 CLK0 F20B1 F21B1 F24B1 F25B1 F36B1 F37B1 F48B1 F49B1
481 CLK0 F32B1 F33B1 F42B1 F43B1
488 CLK0 F30B1 F31B1
495 CLK0 F3B1 F4B1 F5B1 F6B1
502 CLK0 F13B1 F14B1 F16B1 F17B1
|
| /dports/devel/trellis/prjtrellis-5eb0ad87/database/ECP5/tiledata/MIB2_DSP5/ |
| H A D | bits.db | 237 CLK0 -
256 CLK0 -
263 CLK0 -
280 CLK0 -
319 CLK0 -
|
| /dports/devel/trellis/prjtrellis-5eb0ad87/database/ECP5/tiledata/MIB2_DSP8/ |
| H A D | bits.db | 171 CLK0 F63B1 F64B1
190 CLK0 F87B1 F88B1
197 CLK0 F49B1 F66B1
224 CLK0 F63B1 F64B1
231 CLK0 F49B1 F66B1 F87B1 F88B1
252 CLK0 -
|
| /dports/security/john/john-1.9.0-jumbo-1/src/ztex/fpga-bcrypt/ztex_inouttraffic/ |
| H A D | cmt2.v | 26 output CLK0, port
106 .CLK0 (dcm0_clk0),
121 assign CLK0 = dcm0_clk0;
|
| H A D | clocks.v | 96 .CLK0(IFCLK),
|
| /dports/security/john/john-1.9.0-jumbo-1/src/ztex/fpga-descrypt/ztex_inouttraffic/ |
| H A D | cmt2.v | 26 output CLK0, port
107 .CLK0 (dcm0_clk0),
122 assign CLK0 = dcm0_clk0;
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/models/ |
| H A D | DCM_SP.v | 33 CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90,
63 output CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90; port
67 reg CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90; register
579 CLK0 = 0;
829 @(posedge CLK0 or rst_in)
1019 assign CLK0 = 0;
1030 deassign CLK0;
1042 CLK0 <= #(clkout_delay) clk0_out && (clkfb_type != 2'b00);
|
| /dports/cad/yosys/yosys-yosys-0.12/techlibs/gatemate/ |
| H A D | cells_bb.v | 32 output CLK270, CLK180, CLK90, CLK0, CLK_REF_OUT port
44 output CLK270, CLK180, CLK90, CLK0, CLK_REF_OUT port
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b2xxmini/coregen/ |
| H A D | b205_clk_gen.xco | 110 CSET dcm_clk_out1_port=CLK0
113 CSET dcm_clk_out4_port=CLK0
114 CSET dcm_clk_out5_port=CLK0
115 CSET dcm_clk_out6_port=CLK0
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b200/coregen/ |
| H A D | b200_clk_gen.xco | 110 CSET dcm_clk_out1_port=CLK0
113 CSET dcm_clk_out4_port=CLK0
114 CSET dcm_clk_out5_port=CLK0
115 CSET dcm_clk_out6_port=CLK0
|
| /dports/devel/trellis/prjtrellis-5eb0ad87/database/ECP5/tiledata/MIB_DSP2/ |
| H A D | bits.db | 317 CLK0 -
324 CLK0 -
331 CLK0 -
338 CLK0 -
345 CLK0 -
385 CLK0 -
392 CLK0 -
399 CLK0 -
406 CLK0 -
446 CLK0 -
[all …]
|
| /dports/cad/digital/Digital-0.27/src/main/resources/verilog/ |
| H A D | DIG_DCM_SP.v | 38 .CLK0(), // 1-bit output: 0 degree clock output
|
| /dports/devel/trellis/prjtrellis-5eb0ad87/fuzzers/ECP5/073-mult18_config/ |
| H A D | dspconfig.ncl | 16 …${comment} "${mode}:::${settings}:CLK0=#SIG,CLK1=#SIG,CLK2=#SIG,CLK3=#SIG,CE0=#INV,C…
|