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Searched refs:CLK_TOP_MSDC50_2_H_SEL (Results 1 – 9 of 9) sorted by relevance

/dports/multimedia/v4l_compat/linux-5.13-rc2/include/dt-bindings/clock/
H A Dmt8173-clk.h127 #define CLK_TOP_MSDC50_2_H_SEL 117 macro
/dports/multimedia/libv4l/linux-5.13-rc2/include/dt-bindings/clock/
H A Dmt8173-clk.h127 #define CLK_TOP_MSDC50_2_H_SEL 117 macro
/dports/multimedia/v4l-utils/linux-5.13-rc2/include/dt-bindings/clock/
H A Dmt8173-clk.h127 #define CLK_TOP_MSDC50_2_H_SEL 117 macro
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/clk/mediatek/
H A Dclk-mt8173.c590 MUX_GATE(CLK_TOP_MSDC50_2_H_SEL, "msdc50_2_h_sel", msdc50_2_h_parents, 0x00d0, 0, 3, 7),
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/clk/mediatek/
H A Dclk-mt8173.c590 MUX_GATE(CLK_TOP_MSDC50_2_H_SEL, "msdc50_2_h_sel", msdc50_2_h_parents, 0x00d0, 0, 3, 7),
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/clk/mediatek/
H A Dclk-mt8173.c590 MUX_GATE(CLK_TOP_MSDC50_2_H_SEL, "msdc50_2_h_sel", msdc50_2_h_parents, 0x00d0, 0, 3, 7),
/dports/multimedia/v4l-utils/linux-5.13-rc2/arch/arm64/boot/dts/mediatek/
H A Dmt8173.dtsi923 <&topckgen CLK_TOP_MSDC50_2_H_SEL>;
/dports/multimedia/v4l_compat/linux-5.13-rc2/arch/arm64/boot/dts/mediatek/
H A Dmt8173.dtsi923 <&topckgen CLK_TOP_MSDC50_2_H_SEL>;
/dports/multimedia/libv4l/linux-5.13-rc2/arch/arm64/boot/dts/mediatek/
H A Dmt8173.dtsi923 <&topckgen CLK_TOP_MSDC50_2_H_SEL>;