| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/arm/mach-tegra/tegra114/ |
| H A D | clock.c | 664 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
665 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ); in clock_early_init()
674 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8); in clock_early_init()
679 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); in clock_early_init()
684 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); in clock_early_init()
698 writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]); in clock_early_init()
701 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
702 setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena)); in clock_early_init()
742 { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
|
| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/arm/mach-tegra/tegra114/ |
| H A D | clock.c | 664 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
665 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ); in clock_early_init()
674 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8); in clock_early_init()
679 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); in clock_early_init()
684 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); in clock_early_init()
698 writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]); in clock_early_init()
701 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
702 setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena)); in clock_early_init()
742 { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
|
| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/mach-tegra/tegra114/ |
| H A D | clock.c | 667 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
668 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ); in clock_early_init()
677 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8); in clock_early_init()
682 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); in clock_early_init()
687 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); in clock_early_init()
701 writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]); in clock_early_init()
704 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
705 setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena)); in clock_early_init()
745 { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
|
| /dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/arm/mach-tegra/tegra114/ |
| H A D | clock.c | 667 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
668 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ); in clock_early_init()
677 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8); in clock_early_init()
682 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); in clock_early_init()
687 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); in clock_early_init()
701 writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]); in clock_early_init()
704 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
705 setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena)); in clock_early_init()
745 { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
|
| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/mach-tegra/tegra114/ |
| H A D | clock.c | 667 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
668 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ); in clock_early_init()
677 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8); in clock_early_init()
682 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); in clock_early_init()
687 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); in clock_early_init()
701 writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]); in clock_early_init()
704 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
705 setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena)); in clock_early_init()
745 { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
|
| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/mach-tegra/tegra114/ |
| H A D | clock.c | 667 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
668 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ); in clock_early_init()
677 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8); in clock_early_init()
682 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); in clock_early_init()
687 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); in clock_early_init()
701 writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]); in clock_early_init()
704 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
705 setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena)); in clock_early_init()
745 { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
|
| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/arch/arm/mach-tegra/tegra114/ |
| H A D | clock.c | 667 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
668 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ); in clock_early_init()
677 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8); in clock_early_init()
682 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); in clock_early_init()
687 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); in clock_early_init()
701 writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]); in clock_early_init()
704 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
705 setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena)); in clock_early_init()
745 { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/arm/mach-tegra/tegra114/ |
| H A D | clock.c | 667 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
668 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ); in clock_early_init()
677 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8); in clock_early_init()
682 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); in clock_early_init()
687 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); in clock_early_init()
701 writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]); in clock_early_init()
704 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
705 setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena)); in clock_early_init()
745 { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
|
| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/arm/mach-tegra/tegra114/ |
| H A D | clock.c | 667 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
668 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ); in clock_early_init()
677 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8); in clock_early_init()
682 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); in clock_early_init()
687 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); in clock_early_init()
701 writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]); in clock_early_init()
704 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
705 setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena)); in clock_early_init()
745 { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/mach-tegra/tegra114/ |
| H A D | clock.c | 667 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
668 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ); in clock_early_init()
677 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8); in clock_early_init()
682 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); in clock_early_init()
687 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); in clock_early_init()
701 writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]); in clock_early_init()
704 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
705 setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena)); in clock_early_init()
745 { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
|
| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/arm/mach-tegra/tegra114/ |
| H A D | clock.c | 667 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
668 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ); in clock_early_init()
677 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8); in clock_early_init()
682 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); in clock_early_init()
687 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); in clock_early_init()
701 writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]); in clock_early_init()
704 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
705 setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena)); in clock_early_init()
745 { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
|
| /dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/arm/mach-tegra/tegra114/ |
| H A D | clock.c | 667 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
668 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ); in clock_early_init()
677 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8); in clock_early_init()
682 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); in clock_early_init()
687 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); in clock_early_init()
701 writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]); in clock_early_init()
704 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
705 setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena)); in clock_early_init()
745 { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/arm/mach-tegra/tegra114/ |
| H A D | clock.c | 667 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
668 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ); in clock_early_init()
677 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8); in clock_early_init()
682 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); in clock_early_init()
687 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); in clock_early_init()
701 writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]); in clock_early_init()
704 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
705 setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena)); in clock_early_init()
745 { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
|
| /dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/arm/mach-tegra/tegra114/ |
| H A D | clock.c | 667 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
668 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ); in clock_early_init()
677 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8); in clock_early_init()
682 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); in clock_early_init()
687 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); in clock_early_init()
701 writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]); in clock_early_init()
704 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
705 setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena)); in clock_early_init()
745 { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/arm/mach-tegra/tegra114/ |
| H A D | clock.c | 667 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
668 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ); in clock_early_init()
677 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8); in clock_early_init()
682 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); in clock_early_init()
687 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); in clock_early_init()
701 writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]); in clock_early_init()
704 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
705 setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena)); in clock_early_init()
745 { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/mach-tegra/tegra114/ |
| H A D | clock.c | 667 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
668 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ); in clock_early_init()
677 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8); in clock_early_init()
682 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); in clock_early_init()
687 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); in clock_early_init()
701 writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]); in clock_early_init()
704 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
705 setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena)); in clock_early_init()
745 { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
|
| /dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/arm/mach-tegra/tegra114/ |
| H A D | clock.c | 667 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
668 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ); in clock_early_init()
677 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8); in clock_early_init()
682 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); in clock_early_init()
687 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); in clock_early_init()
701 writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]); in clock_early_init()
704 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
705 setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena)); in clock_early_init()
745 { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
|
| /dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/arch/arm/mach-tegra/tegra114/ |
| H A D | clock.c | 667 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
668 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ); in clock_early_init()
677 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8); in clock_early_init()
682 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); in clock_early_init()
687 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); in clock_early_init()
701 writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]); in clock_early_init()
704 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
705 setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena)); in clock_early_init()
745 { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
|
| /dports/sysutils/u-boot-chip/u-boot-2021.07/arch/arm/mach-tegra/tegra114/ |
| H A D | clock.c | 667 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
668 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ); in clock_early_init()
677 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8); in clock_early_init()
682 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); in clock_early_init()
687 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); in clock_early_init()
701 writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]); in clock_early_init()
704 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
705 setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena)); in clock_early_init()
745 { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
|
| /dports/sysutils/u-boot-wandboard/u-boot-2021.07/arch/arm/mach-tegra/tegra114/ |
| H A D | clock.c | 667 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
668 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ); in clock_early_init()
677 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8); in clock_early_init()
682 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); in clock_early_init()
687 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); in clock_early_init()
701 writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]); in clock_early_init()
704 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
705 setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena)); in clock_early_init()
745 { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
|
| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/arm/mach-tegra/tegra114/ |
| H A D | clock.c | 664 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
665 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ); in clock_early_init()
674 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8); in clock_early_init()
679 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); in clock_early_init()
684 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); in clock_early_init()
698 writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]); in clock_early_init()
701 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
702 setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena)); in clock_early_init()
742 { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/arm/mach-tegra/tegra114/ |
| H A D | clock.c | 664 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
665 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ); in clock_early_init()
674 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8); in clock_early_init()
679 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); in clock_early_init()
684 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); in clock_early_init()
698 writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]); in clock_early_init()
701 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
702 setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena)); in clock_early_init()
742 { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
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| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/arm/mach-tegra/tegra114/ |
| H A D | clock.c | 667 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
668 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ); in clock_early_init()
677 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8); in clock_early_init()
682 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); in clock_early_init()
687 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); in clock_early_init()
701 writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]); in clock_early_init()
704 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
705 setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena)); in clock_early_init()
745 { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
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| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/arm/mach-tegra/tegra114/ |
| H A D | clock.c | 667 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
668 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ); in clock_early_init()
677 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8); in clock_early_init()
682 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); in clock_early_init()
687 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); in clock_early_init()
701 writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]); in clock_early_init()
704 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
705 setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena)); in clock_early_init()
745 { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
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| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/arm/mach-tegra/tegra114/ |
| H A D | clock.c | 667 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
668 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ); in clock_early_init()
677 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8); in clock_early_init()
682 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); in clock_early_init()
687 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); in clock_early_init()
701 writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]); in clock_early_init()
704 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
705 setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena)); in clock_early_init()
745 { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
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