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Searched refs:CNTP_CTL (Results 1 – 25 of 39) sorted by relevance

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/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/tests/qtest/
H A Dsse-timer-test.c46 #define CNTP_CTL 0x2c macro
73 writel(TIMER_BASE + CNTP_CTL, 0); in reset_counter_and_timer()
118 g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), ==, 0); in test_timer()
123 writel(TIMER_BASE + CNTP_CTL, 1); in test_timer()
140 g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), ==, 5); in test_timer()
149 g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), ==, 1); in test_timer()
156 g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), ==, 1); in test_timer()
158 g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), ==, 5); in test_timer()
163 g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), ==, 5); in test_timer()
166 g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), ==, 1); in test_timer()
[all …]
/dports/emulators/qemu/qemu-6.2.0/tests/qtest/
H A Dsse-timer-test.c46 #define CNTP_CTL 0x2c macro
73 writel(TIMER_BASE + CNTP_CTL, 0); in reset_counter_and_timer()
118 g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), ==, 0); in test_timer()
123 writel(TIMER_BASE + CNTP_CTL, 1); in test_timer()
140 g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), ==, 5); in test_timer()
149 g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), ==, 1); in test_timer()
156 g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), ==, 1); in test_timer()
158 g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), ==, 5); in test_timer()
163 g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), ==, 5); in test_timer()
166 g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), ==, 1); in test_timer()
[all …]
/dports/emulators/qemu60/qemu-6.0.0/tests/qtest/
H A Dsse-timer-test.c46 #define CNTP_CTL 0x2c macro
73 writel(TIMER_BASE + CNTP_CTL, 0); in reset_counter_and_timer()
118 g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), ==, 0); in test_timer()
123 writel(TIMER_BASE + CNTP_CTL, 1); in test_timer()
140 g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), ==, 5); in test_timer()
149 g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), ==, 1); in test_timer()
156 g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), ==, 1); in test_timer()
158 g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), ==, 5); in test_timer()
163 g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), ==, 5); in test_timer()
166 g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), ==, 1); in test_timer()
[all …]
/dports/emulators/qemu/qemu-6.2.0/hw/timer/
H A Dsse-timer.c57 REG32(CNTP_CTL, 0x2c)
58 FIELD(CNTP_CTL, ENABLE, 0, 1)
59 FIELD(CNTP_CTL, IMASK, 1, 1)
60 FIELD(CNTP_CTL, ISTATUS, 2, 1)
/dports/emulators/qemu60/qemu-6.0.0/hw/timer/
H A Dsse-timer.c57 REG32(CNTP_CTL, 0x2c)
58 FIELD(CNTP_CTL, ENABLE, 0, 1)
59 FIELD(CNTP_CTL, IMASK, 1, 1)
60 FIELD(CNTP_CTL, ISTATUS, 2, 1)
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/hw/timer/
H A Dsse-timer.c57 REG32(CNTP_CTL, 0x2c)
58 FIELD(CNTP_CTL, ENABLE, 0, 1)
59 FIELD(CNTP_CTL, IMASK, 1, 1)
60 FIELD(CNTP_CTL, ISTATUS, 2, 1)
/dports/emulators/qemu42/qemu-4.2.1/roms/edk2/ArmPkg/Library/ArmLib/Arm/
H A DArmV7ArchTimerSupport.asm42 mrc p15, 0, r0, c14, c2, 1 ; Read CNTP_CTL (PL1 Physical Timer Control Register)
46 mcr p15, 0, r0, c14, c2, 1 ; Write to CNTP_CTL (PL1 Physical Timer Control Register)
H A DArmV7ArchTimerSupport.S41 mrc p15, 0, r0, c14, c2, 1 @ Read CNTP_CTL (PL1 Physical Timer Control Register)
45 mcr p15, 0, r0, c14, c2, 1 @ Write to CNTP_CTL (PL1 Physical Timer Control Register)
/dports/emulators/qemu/qemu-6.2.0/roms/edk2/ArmPkg/Library/ArmLib/Arm/
H A DArmV7ArchTimerSupport.asm42 mrc p15, 0, r0, c14, c2, 1 ; Read CNTP_CTL (PL1 Physical Timer Control Register)
46 mcr p15, 0, r0, c14, c2, 1 ; Write to CNTP_CTL (PL1 Physical Timer Control Register)
H A DArmV7ArchTimerSupport.S41 mrc p15, 0, r0, c14, c2, 1 @ Read CNTP_CTL (PL1 Physical Timer Control Register)
45 mcr p15, 0, r0, c14, c2, 1 @ Write to CNTP_CTL (PL1 Physical Timer Control Register)
/dports/emulators/qemu-utils/qemu-4.2.1/roms/edk2/ArmPkg/Library/ArmLib/Arm/
H A DArmV7ArchTimerSupport.asm42 mrc p15, 0, r0, c14, c2, 1 ; Read CNTP_CTL (PL1 Physical Timer Control Register)
46 mcr p15, 0, r0, c14, c2, 1 ; Write to CNTP_CTL (PL1 Physical Timer Control Register)
H A DArmV7ArchTimerSupport.S41 mrc p15, 0, r0, c14, c2, 1 @ Read CNTP_CTL (PL1 Physical Timer Control Register)
45 mcr p15, 0, r0, c14, c2, 1 @ Write to CNTP_CTL (PL1 Physical Timer Control Register)
/dports/emulators/qemu5/qemu-5.2.0/roms/edk2/ArmPkg/Library/ArmLib/Arm/
H A DArmV7ArchTimerSupport.asm42 mrc p15, 0, r0, c14, c2, 1 ; Read CNTP_CTL (PL1 Physical Timer Control Register)
46 mcr p15, 0, r0, c14, c2, 1 ; Write to CNTP_CTL (PL1 Physical Timer Control Register)
H A DArmV7ArchTimerSupport.S41 mrc p15, 0, r0, c14, c2, 1 @ Read CNTP_CTL (PL1 Physical Timer Control Register)
45 mcr p15, 0, r0, c14, c2, 1 @ Write to CNTP_CTL (PL1 Physical Timer Control Register)
/dports/sysutils/uefi-edk2-qemu/edk2-edk2-stable201911/ArmPkg/Library/ArmLib/Arm/
H A DArmV7ArchTimerSupport.asm42 mrc p15, 0, r0, c14, c2, 1 ; Read CNTP_CTL (PL1 Physical Timer Control Register)
46 mcr p15, 0, r0, c14, c2, 1 ; Write to CNTP_CTL (PL1 Physical Timer Control Register)
H A DArmV7ArchTimerSupport.S41 mrc p15, 0, r0, c14, c2, 1 @ Read CNTP_CTL (PL1 Physical Timer Control Register)
45 mcr p15, 0, r0, c14, c2, 1 @ Write to CNTP_CTL (PL1 Physical Timer Control Register)
/dports/sysutils/uefi-edk2-bhyve/edk2-edk2-stable202102/ArmPkg/Library/ArmLib/Arm/
H A DArmV7ArchTimerSupport.asm42 mrc p15, 0, r0, c14, c2, 1 ; Read CNTP_CTL (PL1 Physical Timer Control Register)
46 mcr p15, 0, r0, c14, c2, 1 ; Write to CNTP_CTL (PL1 Physical Timer Control Register)
H A DArmV7ArchTimerSupport.S41 mrc p15, 0, r0, c14, c2, 1 @ Read CNTP_CTL (PL1 Physical Timer Control Register)
45 mcr p15, 0, r0, c14, c2, 1 @ Write to CNTP_CTL (PL1 Physical Timer Control Register)
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/edk2/ArmPkg/Library/ArmLib/Arm/
H A DArmV7ArchTimerSupport.asm42 mrc p15, 0, r0, c14, c2, 1 ; Read CNTP_CTL (PL1 Physical Timer Control Register)
46 mcr p15, 0, r0, c14, c2, 1 ; Write to CNTP_CTL (PL1 Physical Timer Control Register)
H A DArmV7ArchTimerSupport.S41 mrc p15, 0, r0, c14, c2, 1 @ Read CNTP_CTL (PL1 Physical Timer Control Register)
45 mcr p15, 0, r0, c14, c2, 1 @ Write to CNTP_CTL (PL1 Physical Timer Control Register)
/dports/sysutils/edk2/edk2-edk2-stable202102/ArmPkg/Library/ArmLib/Arm/
H A DArmV7ArchTimerSupport.asm42 mrc p15, 0, r0, c14, c2, 1 ; Read CNTP_CTL (PL1 Physical Timer Control Register)
46 mcr p15, 0, r0, c14, c2, 1 ; Write to CNTP_CTL (PL1 Physical Timer Control Register)
H A DArmV7ArchTimerSupport.S41 mrc p15, 0, r0, c14, c2, 1 @ Read CNTP_CTL (PL1 Physical Timer Control Register)
45 mcr p15, 0, r0, c14, c2, 1 @ Write to CNTP_CTL (PL1 Physical Timer Control Register)
/dports/emulators/qemu60/qemu-6.0.0/roms/edk2/ArmPkg/Library/ArmLib/Arm/
H A DArmV7ArchTimerSupport.asm42 mrc p15, 0, r0, c14, c2, 1 ; Read CNTP_CTL (PL1 Physical Timer Control Register)
46 mcr p15, 0, r0, c14, c2, 1 ; Write to CNTP_CTL (PL1 Physical Timer Control Register)
H A DArmV7ArchTimerSupport.S41 mrc p15, 0, r0, c14, c2, 1 @ Read CNTP_CTL (PL1 Physical Timer Control Register)
45 mcr p15, 0, r0, c14, c2, 1 @ Write to CNTP_CTL (PL1 Physical Timer Control Register)
/dports/sysutils/uefi-edk2-bhyve-csm/uefi-edk2-aa8d718/ArmPkg/Library/ArmLib/ArmV7/
H A DArmV7ArchTimerSupport.asm68 mrc p15, 0, r0, c14, c2, 1 ; Read CNTP_CTL (PL1 Physical Timer Control Register)
72 mcr p15, 0, r0, c14, c2, 1 ; Write to CNTP_CTL (PL1 Physical Timer Control Register)

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