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Searched refs:CPM_CPCCR (Results 1 – 25 of 62) sorted by relevance

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/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/mips/mach-jz47xx/jz4780/
H A Dpll.c14 #define CPM_CPCCR 0x00 macro
405 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0x00ffffff, clk_ctrl); in cpu_mux_select()
419 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0xff << 24, clk_ctrl); in cpu_mux_select()
485 u32 cpccr = readl(cpm_regs + CPM_CPCCR); in jz4780_clk_get_efuse_clk()
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/mips/mach-jz47xx/jz4780/
H A Dpll.c14 #define CPM_CPCCR 0x00 macro
405 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0x00ffffff, clk_ctrl); in cpu_mux_select()
419 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0xff << 24, clk_ctrl); in cpu_mux_select()
485 u32 cpccr = readl(cpm_regs + CPM_CPCCR); in jz4780_clk_get_efuse_clk()
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/
H A Dpll.c16 #define CPM_CPCCR 0x00 macro
407 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0x00ffffff, clk_ctrl); in cpu_mux_select()
421 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0xff << 24, clk_ctrl); in cpu_mux_select()
487 u32 cpccr = readl(cpm_regs + CPM_CPCCR); in jz4780_clk_get_efuse_clk()
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/
H A Dpll.c16 #define CPM_CPCCR 0x00 macro
407 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0x00ffffff, clk_ctrl); in cpu_mux_select()
421 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0xff << 24, clk_ctrl); in cpu_mux_select()
487 u32 cpccr = readl(cpm_regs + CPM_CPCCR); in jz4780_clk_get_efuse_clk()
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/
H A Dpll.c16 #define CPM_CPCCR 0x00 macro
407 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0x00ffffff, clk_ctrl); in cpu_mux_select()
421 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0xff << 24, clk_ctrl); in cpu_mux_select()
487 u32 cpccr = readl(cpm_regs + CPM_CPCCR); in jz4780_clk_get_efuse_clk()
/dports/sysutils/u-boot-chip/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/
H A Dpll.c16 #define CPM_CPCCR 0x00 macro
407 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0x00ffffff, clk_ctrl); in cpu_mux_select()
421 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0xff << 24, clk_ctrl); in cpu_mux_select()
487 u32 cpccr = readl(cpm_regs + CPM_CPCCR); in jz4780_clk_get_efuse_clk()
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/
H A Dpll.c16 #define CPM_CPCCR 0x00 macro
407 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0x00ffffff, clk_ctrl); in cpu_mux_select()
421 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0xff << 24, clk_ctrl); in cpu_mux_select()
487 u32 cpccr = readl(cpm_regs + CPM_CPCCR); in jz4780_clk_get_efuse_clk()
/dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/
H A Dpll.c16 #define CPM_CPCCR 0x00 macro
407 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0x00ffffff, clk_ctrl); in cpu_mux_select()
421 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0xff << 24, clk_ctrl); in cpu_mux_select()
487 u32 cpccr = readl(cpm_regs + CPM_CPCCR); in jz4780_clk_get_efuse_clk()
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/
H A Dpll.c16 #define CPM_CPCCR 0x00 macro
407 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0x00ffffff, clk_ctrl); in cpu_mux_select()
421 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0xff << 24, clk_ctrl); in cpu_mux_select()
487 u32 cpccr = readl(cpm_regs + CPM_CPCCR); in jz4780_clk_get_efuse_clk()
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/
H A Dpll.c16 #define CPM_CPCCR 0x00 macro
407 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0x00ffffff, clk_ctrl); in cpu_mux_select()
421 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0xff << 24, clk_ctrl); in cpu_mux_select()
487 u32 cpccr = readl(cpm_regs + CPM_CPCCR); in jz4780_clk_get_efuse_clk()
/dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/
H A Dpll.c16 #define CPM_CPCCR 0x00 macro
407 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0x00ffffff, clk_ctrl); in cpu_mux_select()
421 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0xff << 24, clk_ctrl); in cpu_mux_select()
487 u32 cpccr = readl(cpm_regs + CPM_CPCCR); in jz4780_clk_get_efuse_clk()
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/
H A Dpll.c16 #define CPM_CPCCR 0x00 macro
407 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0x00ffffff, clk_ctrl); in cpu_mux_select()
421 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0xff << 24, clk_ctrl); in cpu_mux_select()
487 u32 cpccr = readl(cpm_regs + CPM_CPCCR); in jz4780_clk_get_efuse_clk()
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/
H A Dpll.c16 #define CPM_CPCCR 0x00 macro
407 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0x00ffffff, clk_ctrl); in cpu_mux_select()
421 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0xff << 24, clk_ctrl); in cpu_mux_select()
487 u32 cpccr = readl(cpm_regs + CPM_CPCCR); in jz4780_clk_get_efuse_clk()
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/
H A Dpll.c16 #define CPM_CPCCR 0x00 macro
407 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0x00ffffff, clk_ctrl); in cpu_mux_select()
421 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0xff << 24, clk_ctrl); in cpu_mux_select()
487 u32 cpccr = readl(cpm_regs + CPM_CPCCR); in jz4780_clk_get_efuse_clk()
/dports/sysutils/u-boot-wandboard/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/
H A Dpll.c16 #define CPM_CPCCR 0x00 macro
407 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0x00ffffff, clk_ctrl); in cpu_mux_select()
421 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0xff << 24, clk_ctrl); in cpu_mux_select()
487 u32 cpccr = readl(cpm_regs + CPM_CPCCR); in jz4780_clk_get_efuse_clk()
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/mips/mach-jz47xx/jz4780/
H A Dpll.c14 #define CPM_CPCCR 0x00 macro
405 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0x00ffffff, clk_ctrl); in cpu_mux_select()
419 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0xff << 24, clk_ctrl); in cpu_mux_select()
485 u32 cpccr = readl(cpm_regs + CPM_CPCCR); in jz4780_clk_get_efuse_clk()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/mips/mach-jz47xx/jz4780/
H A Dpll.c14 #define CPM_CPCCR 0x00
405 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0x00ffffff, clk_ctrl);
419 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0xff << 24, clk_ctrl);
485 u32 cpccr = readl(cpm_regs + CPM_CPCCR);
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/
H A Dpll.c16 #define CPM_CPCCR 0x00 macro
407 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0x00ffffff, clk_ctrl); in cpu_mux_select()
421 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0xff << 24, clk_ctrl); in cpu_mux_select()
487 u32 cpccr = readl(cpm_regs + CPM_CPCCR); in jz4780_clk_get_efuse_clk()
/dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/
H A Dpll.c16 #define CPM_CPCCR 0x00 macro
407 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0x00ffffff, clk_ctrl); in cpu_mux_select()
421 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0xff << 24, clk_ctrl); in cpu_mux_select()
487 u32 cpccr = readl(cpm_regs + CPM_CPCCR); in jz4780_clk_get_efuse_clk()
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/
H A Dpll.c16 #define CPM_CPCCR 0x00 macro
407 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0x00ffffff, clk_ctrl); in cpu_mux_select()
421 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0xff << 24, clk_ctrl); in cpu_mux_select()
487 u32 cpccr = readl(cpm_regs + CPM_CPCCR); in jz4780_clk_get_efuse_clk()
/dports/sysutils/u-boot-pandaboard/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/
H A Dpll.c16 #define CPM_CPCCR 0x00 macro
407 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0x00ffffff, clk_ctrl); in cpu_mux_select()
421 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0xff << 24, clk_ctrl); in cpu_mux_select()
487 u32 cpccr = readl(cpm_regs + CPM_CPCCR); in jz4780_clk_get_efuse_clk()
/dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/
H A Dpll.c16 #define CPM_CPCCR 0x00 macro
407 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0x00ffffff, clk_ctrl); in cpu_mux_select()
421 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0xff << 24, clk_ctrl); in cpu_mux_select()
487 u32 cpccr = readl(cpm_regs + CPM_CPCCR); in jz4780_clk_get_efuse_clk()
/dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/
H A Dpll.c16 #define CPM_CPCCR 0x00 macro
407 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0x00ffffff, clk_ctrl); in cpu_mux_select()
421 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0xff << 24, clk_ctrl); in cpu_mux_select()
487 u32 cpccr = readl(cpm_regs + CPM_CPCCR); in jz4780_clk_get_efuse_clk()
/dports/sysutils/u-boot-pcduino3/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/
H A Dpll.c16 #define CPM_CPCCR 0x00 macro
407 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0x00ffffff, clk_ctrl); in cpu_mux_select()
421 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0xff << 24, clk_ctrl); in cpu_mux_select()
487 u32 cpccr = readl(cpm_regs + CPM_CPCCR); in jz4780_clk_get_efuse_clk()
/dports/sysutils/u-boot-pine-h64/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/
H A Dpll.c16 #define CPM_CPCCR 0x00
407 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0x00ffffff, clk_ctrl);
421 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0xff << 24, clk_ctrl);
487 u32 cpccr = readl(cpm_regs + CPM_CPCCR);

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