/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/mips/mach-jz47xx/jz4780/ |
H A D | pll.c | 143 #define CPM_DDRCDR_CE_DDR BIT(29) macro 429 writel(selectplls[pll] | CPM_DDRCDR_CE_DDR | (JZ4780_SYS_MEM_DIV - 1), in ddr_mux_select()
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/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/mips/mach-jz47xx/jz4780/ |
H A D | pll.c | 143 #define CPM_DDRCDR_CE_DDR BIT(29) macro 429 writel(selectplls[pll] | CPM_DDRCDR_CE_DDR | (JZ4780_SYS_MEM_DIV - 1), in ddr_mux_select()
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/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/ |
H A D | pll.c | 145 #define CPM_DDRCDR_CE_DDR BIT(29) macro 431 writel(selectplls[pll] | CPM_DDRCDR_CE_DDR | (JZ4780_SYS_MEM_DIV - 1), in ddr_mux_select()
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/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/ |
H A D | pll.c | 145 #define CPM_DDRCDR_CE_DDR BIT(29) macro 431 writel(selectplls[pll] | CPM_DDRCDR_CE_DDR | (JZ4780_SYS_MEM_DIV - 1), in ddr_mux_select()
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/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/ |
H A D | pll.c | 145 #define CPM_DDRCDR_CE_DDR BIT(29) macro 431 writel(selectplls[pll] | CPM_DDRCDR_CE_DDR | (JZ4780_SYS_MEM_DIV - 1), in ddr_mux_select()
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/dports/sysutils/u-boot-chip/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/ |
H A D | pll.c | 145 #define CPM_DDRCDR_CE_DDR BIT(29) macro 431 writel(selectplls[pll] | CPM_DDRCDR_CE_DDR | (JZ4780_SYS_MEM_DIV - 1), in ddr_mux_select()
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/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/ |
H A D | pll.c | 145 #define CPM_DDRCDR_CE_DDR BIT(29) macro 431 writel(selectplls[pll] | CPM_DDRCDR_CE_DDR | (JZ4780_SYS_MEM_DIV - 1), in ddr_mux_select()
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/dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/ |
H A D | pll.c | 145 #define CPM_DDRCDR_CE_DDR BIT(29) macro 431 writel(selectplls[pll] | CPM_DDRCDR_CE_DDR | (JZ4780_SYS_MEM_DIV - 1), in ddr_mux_select()
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/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/ |
H A D | pll.c | 145 #define CPM_DDRCDR_CE_DDR BIT(29) macro 431 writel(selectplls[pll] | CPM_DDRCDR_CE_DDR | (JZ4780_SYS_MEM_DIV - 1), in ddr_mux_select()
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/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/ |
H A D | pll.c | 145 #define CPM_DDRCDR_CE_DDR BIT(29) macro 431 writel(selectplls[pll] | CPM_DDRCDR_CE_DDR | (JZ4780_SYS_MEM_DIV - 1), in ddr_mux_select()
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/dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/ |
H A D | pll.c | 145 #define CPM_DDRCDR_CE_DDR BIT(29) macro 431 writel(selectplls[pll] | CPM_DDRCDR_CE_DDR | (JZ4780_SYS_MEM_DIV - 1), in ddr_mux_select()
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/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/ |
H A D | pll.c | 145 #define CPM_DDRCDR_CE_DDR BIT(29) macro 431 writel(selectplls[pll] | CPM_DDRCDR_CE_DDR | (JZ4780_SYS_MEM_DIV - 1), in ddr_mux_select()
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/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/ |
H A D | pll.c | 145 #define CPM_DDRCDR_CE_DDR BIT(29) macro 431 writel(selectplls[pll] | CPM_DDRCDR_CE_DDR | (JZ4780_SYS_MEM_DIV - 1), in ddr_mux_select()
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/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/ |
H A D | pll.c | 145 #define CPM_DDRCDR_CE_DDR BIT(29) macro 431 writel(selectplls[pll] | CPM_DDRCDR_CE_DDR | (JZ4780_SYS_MEM_DIV - 1), in ddr_mux_select()
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/dports/sysutils/u-boot-wandboard/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/ |
H A D | pll.c | 145 #define CPM_DDRCDR_CE_DDR BIT(29) macro 431 writel(selectplls[pll] | CPM_DDRCDR_CE_DDR | (JZ4780_SYS_MEM_DIV - 1), in ddr_mux_select()
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/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/mips/mach-jz47xx/jz4780/ |
H A D | pll.c | 143 #define CPM_DDRCDR_CE_DDR BIT(29) macro 429 writel(selectplls[pll] | CPM_DDRCDR_CE_DDR | (JZ4780_SYS_MEM_DIV - 1), in ddr_mux_select()
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/mips/mach-jz47xx/jz4780/ |
H A D | pll.c | 143 #define CPM_DDRCDR_CE_DDR BIT(29) 429 writel(selectplls[pll] | CPM_DDRCDR_CE_DDR | (JZ4780_SYS_MEM_DIV - 1),
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/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/ |
H A D | pll.c | 145 #define CPM_DDRCDR_CE_DDR BIT(29) macro 431 writel(selectplls[pll] | CPM_DDRCDR_CE_DDR | (JZ4780_SYS_MEM_DIV - 1), in ddr_mux_select()
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/dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/ |
H A D | pll.c | 145 #define CPM_DDRCDR_CE_DDR BIT(29) macro 431 writel(selectplls[pll] | CPM_DDRCDR_CE_DDR | (JZ4780_SYS_MEM_DIV - 1), in ddr_mux_select()
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/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/ |
H A D | pll.c | 145 #define CPM_DDRCDR_CE_DDR BIT(29) macro 431 writel(selectplls[pll] | CPM_DDRCDR_CE_DDR | (JZ4780_SYS_MEM_DIV - 1), in ddr_mux_select()
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/dports/sysutils/u-boot-pandaboard/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/ |
H A D | pll.c | 145 #define CPM_DDRCDR_CE_DDR BIT(29) macro 431 writel(selectplls[pll] | CPM_DDRCDR_CE_DDR | (JZ4780_SYS_MEM_DIV - 1), in ddr_mux_select()
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/dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/ |
H A D | pll.c | 145 #define CPM_DDRCDR_CE_DDR BIT(29) macro 431 writel(selectplls[pll] | CPM_DDRCDR_CE_DDR | (JZ4780_SYS_MEM_DIV - 1), in ddr_mux_select()
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/dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/ |
H A D | pll.c | 145 #define CPM_DDRCDR_CE_DDR BIT(29) macro 431 writel(selectplls[pll] | CPM_DDRCDR_CE_DDR | (JZ4780_SYS_MEM_DIV - 1), in ddr_mux_select()
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/dports/sysutils/u-boot-pcduino3/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/ |
H A D | pll.c | 145 #define CPM_DDRCDR_CE_DDR BIT(29) macro 431 writel(selectplls[pll] | CPM_DDRCDR_CE_DDR | (JZ4780_SYS_MEM_DIV - 1), in ddr_mux_select()
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/dports/sysutils/u-boot-pine-h64/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/ |
H A D | pll.c | 145 #define CPM_DDRCDR_CE_DDR BIT(29) 431 writel(selectplls[pll] | CPM_DDRCDR_CE_DDR | (JZ4780_SYS_MEM_DIV - 1),
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