| /dports/misc/rump/buildrump.sh-b914579/src/sys/external/bsd/drm2/dist/drm/radeon/ |
| H A D | cikd.h | 1313 #define CP_ME1_PIPE0_INT_CNTL 0xC214 macro
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| H A D | cik.c | 6765 WREG32(CP_ME1_PIPE0_INT_CNTL, 0); in cik_disable_interrupt_state()
6947 cp_m1p0 = RREG32(CP_ME1_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7133 WREG32(CP_ME1_PIPE0_INT_CNTL, cp_m1p0); in cik_irq_set()
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| /dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/radeon/ |
| H A D | cikd.h | 1358 #define CP_ME1_PIPE0_INT_CNTL 0xC214 macro
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| H A D | cik.c | 6868 WREG32(CP_ME1_PIPE0_INT_CNTL, 0); in cik_disable_interrupt_state()
7051 cp_m1p0 = RREG32(CP_ME1_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7222 WREG32(CP_ME1_PIPE0_INT_CNTL, cp_m1p0); in cik_irq_set()
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| /dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/radeon/ |
| H A D | cikd.h | 1358 #define CP_ME1_PIPE0_INT_CNTL 0xC214 macro
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| H A D | cik.c | 6868 WREG32(CP_ME1_PIPE0_INT_CNTL, 0); in cik_disable_interrupt_state()
7051 cp_m1p0 = RREG32(CP_ME1_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7222 WREG32(CP_ME1_PIPE0_INT_CNTL, cp_m1p0); in cik_irq_set()
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| /dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/radeon/ |
| H A D | cikd.h | 1358 #define CP_ME1_PIPE0_INT_CNTL 0xC214 macro
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| H A D | cik.c | 6868 WREG32(CP_ME1_PIPE0_INT_CNTL, 0); in cik_disable_interrupt_state()
7051 cp_m1p0 = RREG32(CP_ME1_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7222 WREG32(CP_ME1_PIPE0_INT_CNTL, cp_m1p0); in cik_irq_set()
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| /dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/amdgpu/ |
| H A D | gfx_v9_0.c | 5729 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v9_0_set_compute_eop_interrupt_state()
5735 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v9_0_set_compute_eop_interrupt_state()
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| H A D | gfx_v10_0.c | 8675 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v10_0_set_compute_eop_interrupt_state()
8681 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v10_0_set_compute_eop_interrupt_state()
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| H A D | gfx_v8_0.c | 6590 WREG32_FIELD(CP_ME1_PIPE0_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, in gfx_v8_0_set_cp_ecc_int_state()
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| /dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/amdgpu/ |
| H A D | gfx_v9_0.c | 5729 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v9_0_set_compute_eop_interrupt_state()
5735 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v9_0_set_compute_eop_interrupt_state()
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| H A D | gfx_v10_0.c | 8675 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v10_0_set_compute_eop_interrupt_state()
8681 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v10_0_set_compute_eop_interrupt_state()
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| H A D | gfx_v8_0.c | 6590 WREG32_FIELD(CP_ME1_PIPE0_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, in gfx_v8_0_set_cp_ecc_int_state()
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| /dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/amdgpu/ |
| H A D | gfx_v9_0.c | 5729 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v9_0_set_compute_eop_interrupt_state()
5735 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v9_0_set_compute_eop_interrupt_state()
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| H A D | gfx_v10_0.c | 8675 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v10_0_set_compute_eop_interrupt_state()
8681 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v10_0_set_compute_eop_interrupt_state()
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| H A D | gfx_v8_0.c | 6590 WREG32_FIELD(CP_ME1_PIPE0_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, in gfx_v8_0_set_cp_ecc_int_state()
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