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Searched refs:CP_ME1_PIPE1_INT_CNTL (Results 1 – 11 of 11) sorted by relevance

/dports/misc/rump/buildrump.sh-b914579/src/sys/external/bsd/drm2/dist/drm/radeon/
H A Dcikd.h1314 #define CP_ME1_PIPE1_INT_CNTL 0xC218 macro
H A Dcik.c6766 WREG32(CP_ME1_PIPE1_INT_CNTL, 0); in cik_disable_interrupt_state()
6948 cp_m1p1 = RREG32(CP_ME1_PIPE1_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7134 WREG32(CP_ME1_PIPE1_INT_CNTL, cp_m1p1); in cik_irq_set()
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/radeon/
H A Dcikd.h1359 #define CP_ME1_PIPE1_INT_CNTL 0xC218 macro
H A Dcik.c6869 WREG32(CP_ME1_PIPE1_INT_CNTL, 0); in cik_disable_interrupt_state()
7052 cp_m1p1 = RREG32(CP_ME1_PIPE1_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7223 WREG32(CP_ME1_PIPE1_INT_CNTL, cp_m1p1); in cik_irq_set()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/radeon/
H A Dcikd.h1359 #define CP_ME1_PIPE1_INT_CNTL 0xC218 macro
H A Dcik.c6869 WREG32(CP_ME1_PIPE1_INT_CNTL, 0); in cik_disable_interrupt_state()
7052 cp_m1p1 = RREG32(CP_ME1_PIPE1_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7223 WREG32(CP_ME1_PIPE1_INT_CNTL, cp_m1p1); in cik_irq_set()
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/radeon/
H A Dcikd.h1359 #define CP_ME1_PIPE1_INT_CNTL 0xC218 macro
H A Dcik.c6869 WREG32(CP_ME1_PIPE1_INT_CNTL, 0); in cik_disable_interrupt_state()
7052 cp_m1p1 = RREG32(CP_ME1_PIPE1_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7223 WREG32(CP_ME1_PIPE1_INT_CNTL, cp_m1p1); in cik_irq_set()
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v8_0.c6592 WREG32_FIELD(CP_ME1_PIPE1_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, in gfx_v8_0_set_cp_ecc_int_state()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v8_0.c6592 WREG32_FIELD(CP_ME1_PIPE1_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, in gfx_v8_0_set_cp_ecc_int_state()
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v8_0.c6592 WREG32_FIELD(CP_ME1_PIPE1_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, in gfx_v8_0_set_cp_ecc_int_state()