Searched refs:CP_ME2_PIPE1_INT_CNTL (Results 1 – 11 of 11) sorted by relevance
/dports/misc/rump/buildrump.sh-b914579/src/sys/external/bsd/drm2/dist/drm/radeon/ |
H A D | cikd.h | 1318 #define CP_ME2_PIPE1_INT_CNTL 0xC228 macro
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H A D | cik.c | 6770 WREG32(CP_ME2_PIPE1_INT_CNTL, 0); in cik_disable_interrupt_state() 6952 cp_m2p1 = RREG32(CP_ME2_PIPE1_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set() 7138 WREG32(CP_ME2_PIPE1_INT_CNTL, cp_m2p1); in cik_irq_set()
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/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/radeon/ |
H A D | cikd.h | 1363 #define CP_ME2_PIPE1_INT_CNTL 0xC228 macro
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H A D | cik.c | 6873 WREG32(CP_ME2_PIPE1_INT_CNTL, 0); in cik_disable_interrupt_state() 7056 cp_m2p1 = RREG32(CP_ME2_PIPE1_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set() 7227 WREG32(CP_ME2_PIPE1_INT_CNTL, cp_m2p1); in cik_irq_set()
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/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/radeon/ |
H A D | cikd.h | 1363 #define CP_ME2_PIPE1_INT_CNTL 0xC228 macro
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H A D | cik.c | 6873 WREG32(CP_ME2_PIPE1_INT_CNTL, 0); in cik_disable_interrupt_state() 7056 cp_m2p1 = RREG32(CP_ME2_PIPE1_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set() 7227 WREG32(CP_ME2_PIPE1_INT_CNTL, cp_m2p1); in cik_irq_set()
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/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/radeon/ |
H A D | cikd.h | 1363 #define CP_ME2_PIPE1_INT_CNTL 0xC228 macro
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H A D | cik.c | 6873 WREG32(CP_ME2_PIPE1_INT_CNTL, 0); in cik_disable_interrupt_state() 7056 cp_m2p1 = RREG32(CP_ME2_PIPE1_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set() 7227 WREG32(CP_ME2_PIPE1_INT_CNTL, cp_m2p1); in cik_irq_set()
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/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/amdgpu/ |
H A D | gfx_v8_0.c | 6600 WREG32_FIELD(CP_ME2_PIPE1_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, in gfx_v8_0_set_cp_ecc_int_state()
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/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/amdgpu/ |
H A D | gfx_v8_0.c | 6600 WREG32_FIELD(CP_ME2_PIPE1_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, in gfx_v8_0_set_cp_ecc_int_state()
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/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/amdgpu/ |
H A D | gfx_v8_0.c | 6600 WREG32_FIELD(CP_ME2_PIPE1_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, in gfx_v8_0_set_cp_ecc_int_state()
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