CRTC_VSYNC_STRT_WID_VAL (reference) in projects: dports

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Searched refs:CRTC_VSYNC_STRT_WID_VAL (Results 1 – 25 of 70) sorted by relevance

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/dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/video/
H A D	ati_radeon_fb.c	59 #define CRTC_VSYNC_STRT_WID_VAL(vsync_srtr, vsync_wid) \ macro 395 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(1025,3); in radeon_setmode_9200() 428 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(769,3); in radeon_setmode_9200() 434 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(771,6) \| CRTC_V_SYNC_POL; in radeon_setmode_9200() 459 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,3); in radeon_setmode_9200() 464 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,4); in radeon_setmode_9200() 490 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(481,3) \| CRTC_V_SYNC_POL; in radeon_setmode_9200() 496 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(491,2) \| CRTC_V_SYNC_POL; in radeon_setmode_9200()
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/drivers/video/
H A D	ati_radeon_fb.c	57 #define CRTC_VSYNC_STRT_WID_VAL(vsync_srtr, vsync_wid) \ macro 393 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(1025,3); in radeon_setmode_9200() 426 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(769,3); in radeon_setmode_9200() 432 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(771,6) \| CRTC_V_SYNC_POL; in radeon_setmode_9200() 457 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,3); in radeon_setmode_9200() 462 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,4); in radeon_setmode_9200() 488 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(481,3) \| CRTC_V_SYNC_POL; in radeon_setmode_9200() 494 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(491,2) \| CRTC_V_SYNC_POL; in radeon_setmode_9200()
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/drivers/video/
H A D	ati_radeon_fb.c	79 #define CRTC_VSYNC_STRT_WID_VAL(vsync_srtr, vsync_wid) \ macro 415 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(1025,3); in radeon_setmode_9200() 448 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(769,3); in radeon_setmode_9200() 454 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(771,6) \| CRTC_V_SYNC_POL; in radeon_setmode_9200() 479 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,3); in radeon_setmode_9200() 484 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,4); in radeon_setmode_9200() 510 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(481,3) \| CRTC_V_SYNC_POL; in radeon_setmode_9200() 516 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(491,2) \| CRTC_V_SYNC_POL; in radeon_setmode_9200()
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/drivers/video/
H A D	ati_radeon_fb.c	57 #define CRTC_VSYNC_STRT_WID_VAL(vsync_srtr, vsync_wid) \ macro 393 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(1025,3); in radeon_setmode_9200() 426 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(769,3); in radeon_setmode_9200() 432 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(771,6) \| CRTC_V_SYNC_POL; in radeon_setmode_9200() 457 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,3); in radeon_setmode_9200() 462 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,4); in radeon_setmode_9200() 488 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(481,3) \| CRTC_V_SYNC_POL; in radeon_setmode_9200() 494 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(491,2) \| CRTC_V_SYNC_POL; in radeon_setmode_9200()
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/drivers/video/
H A D	ati_radeon_fb.c	79 #define CRTC_VSYNC_STRT_WID_VAL(vsync_srtr, vsync_wid) \ macro 415 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(1025,3); in radeon_setmode_9200() 448 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(769,3); in radeon_setmode_9200() 454 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(771,6) \| CRTC_V_SYNC_POL; in radeon_setmode_9200() 479 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,3); in radeon_setmode_9200() 484 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,4); in radeon_setmode_9200() 510 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(481,3) \| CRTC_V_SYNC_POL; in radeon_setmode_9200() 516 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(491,2) \| CRTC_V_SYNC_POL; in radeon_setmode_9200()
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/video/
H A D	ati_radeon_fb.c	59 #define CRTC_VSYNC_STRT_WID_VAL(vsync_srtr, vsync_wid) \ macro 395 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(1025,3); in radeon_setmode_9200() 428 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(769,3); in radeon_setmode_9200() 434 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(771,6) \| CRTC_V_SYNC_POL; in radeon_setmode_9200() 459 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,3); in radeon_setmode_9200() 464 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,4); in radeon_setmode_9200() 490 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(481,3) \| CRTC_V_SYNC_POL; in radeon_setmode_9200() 496 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(491,2) \| CRTC_V_SYNC_POL; in radeon_setmode_9200()
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/video/
H A D	ati_radeon_fb.c	59 #define CRTC_VSYNC_STRT_WID_VAL(vsync_srtr, vsync_wid) \ macro 395 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(1025,3); in radeon_setmode_9200() 428 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(769,3); in radeon_setmode_9200() 434 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(771,6) \| CRTC_V_SYNC_POL; in radeon_setmode_9200() 459 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,3); in radeon_setmode_9200() 464 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,4); in radeon_setmode_9200() 490 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(481,3) \| CRTC_V_SYNC_POL; in radeon_setmode_9200() 496 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(491,2) \| CRTC_V_SYNC_POL; in radeon_setmode_9200()
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/drivers/video/
H A D	ati_radeon_fb.c	79 #define CRTC_VSYNC_STRT_WID_VAL(vsync_srtr, vsync_wid) \ macro 415 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(1025,3); in radeon_setmode_9200() 448 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(769,3); in radeon_setmode_9200() 454 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(771,6) \| CRTC_V_SYNC_POL; in radeon_setmode_9200() 479 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,3); in radeon_setmode_9200() 484 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,4); in radeon_setmode_9200() 510 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(481,3) \| CRTC_V_SYNC_POL; in radeon_setmode_9200() 516 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(491,2) \| CRTC_V_SYNC_POL; in radeon_setmode_9200()
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/video/
H A D	ati_radeon_fb.c	59 #define CRTC_VSYNC_STRT_WID_VAL(vsync_srtr, vsync_wid) \ macro 395 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(1025,3); in radeon_setmode_9200() 428 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(769,3); in radeon_setmode_9200() 434 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(771,6) \| CRTC_V_SYNC_POL; in radeon_setmode_9200() 459 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,3); in radeon_setmode_9200() 464 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,4); in radeon_setmode_9200() 490 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(481,3) \| CRTC_V_SYNC_POL; in radeon_setmode_9200() 496 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(491,2) \| CRTC_V_SYNC_POL; in radeon_setmode_9200()
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/video/
H A D	ati_radeon_fb.c	59 #define CRTC_VSYNC_STRT_WID_VAL(vsync_srtr, vsync_wid) \ macro 395 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(1025,3); in radeon_setmode_9200() 428 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(769,3); in radeon_setmode_9200() 434 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(771,6) \| CRTC_V_SYNC_POL; in radeon_setmode_9200() 459 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,3); in radeon_setmode_9200() 464 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,4); in radeon_setmode_9200() 490 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(481,3) \| CRTC_V_SYNC_POL; in radeon_setmode_9200() 496 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(491,2) \| CRTC_V_SYNC_POL; in radeon_setmode_9200()
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/video/
H A D	ati_radeon_fb.c	59 #define CRTC_VSYNC_STRT_WID_VAL(vsync_srtr, vsync_wid) \ macro 395 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(1025,3); in radeon_setmode_9200() 428 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(769,3); in radeon_setmode_9200() 434 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(771,6) \| CRTC_V_SYNC_POL; in radeon_setmode_9200() 459 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,3); in radeon_setmode_9200() 464 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,4); in radeon_setmode_9200() 490 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(481,3) \| CRTC_V_SYNC_POL; in radeon_setmode_9200() 496 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(491,2) \| CRTC_V_SYNC_POL; in radeon_setmode_9200()
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/video/
H A D	ati_radeon_fb.c	59 #define CRTC_VSYNC_STRT_WID_VAL(vsync_srtr, vsync_wid) \ macro 395 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(1025,3); in radeon_setmode_9200() 428 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(769,3); in radeon_setmode_9200() 434 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(771,6) \| CRTC_V_SYNC_POL; in radeon_setmode_9200() 459 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,3); in radeon_setmode_9200() 464 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,4); in radeon_setmode_9200() 490 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(481,3) \| CRTC_V_SYNC_POL; in radeon_setmode_9200() 496 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(491,2) \| CRTC_V_SYNC_POL; in radeon_setmode_9200()
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/video/
H A D	ati_radeon_fb.c	59 #define CRTC_VSYNC_STRT_WID_VAL(vsync_srtr, vsync_wid) \ macro 395 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(1025,3); in radeon_setmode_9200() 428 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(769,3); in radeon_setmode_9200() 434 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(771,6) \| CRTC_V_SYNC_POL; in radeon_setmode_9200() 459 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,3); in radeon_setmode_9200() 464 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,4); in radeon_setmode_9200() 490 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(481,3) \| CRTC_V_SYNC_POL; in radeon_setmode_9200() 496 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(491,2) \| CRTC_V_SYNC_POL; in radeon_setmode_9200()
/dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/video/
H A D	ati_radeon_fb.c	59 #define CRTC_VSYNC_STRT_WID_VAL(vsync_srtr, vsync_wid) \ macro 395 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(1025,3); in radeon_setmode_9200() 428 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(769,3); in radeon_setmode_9200() 434 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(771,6) \| CRTC_V_SYNC_POL; in radeon_setmode_9200() 459 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,3); in radeon_setmode_9200() 464 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,4); in radeon_setmode_9200() 490 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(481,3) \| CRTC_V_SYNC_POL; in radeon_setmode_9200() 496 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(491,2) \| CRTC_V_SYNC_POL; in radeon_setmode_9200()
/dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/video/
H A D	ati_radeon_fb.c	59 #define CRTC_VSYNC_STRT_WID_VAL(vsync_srtr, vsync_wid) \ macro 395 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(1025,3); in radeon_setmode_9200() 428 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(769,3); in radeon_setmode_9200() 434 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(771,6) \| CRTC_V_SYNC_POL; in radeon_setmode_9200() 459 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,3); in radeon_setmode_9200() 464 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,4); in radeon_setmode_9200() 490 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(481,3) \| CRTC_V_SYNC_POL; in radeon_setmode_9200() 496 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(491,2) \| CRTC_V_SYNC_POL; in radeon_setmode_9200()
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/video/
H A D	ati_radeon_fb.c	59 #define CRTC_VSYNC_STRT_WID_VAL(vsync_srtr, vsync_wid) \ macro 395 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(1025,3); in radeon_setmode_9200() 428 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(769,3); in radeon_setmode_9200() 434 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(771,6) \| CRTC_V_SYNC_POL; in radeon_setmode_9200() 459 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,3); in radeon_setmode_9200() 464 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,4); in radeon_setmode_9200() 490 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(481,3) \| CRTC_V_SYNC_POL; in radeon_setmode_9200() 496 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(491,2) \| CRTC_V_SYNC_POL; in radeon_setmode_9200()
/dports/sysutils/u-boot-pinebookpro/u-boot-2021.07/drivers/video/
H A D	ati_radeon_fb.c	59 #define CRTC_VSYNC_STRT_WID_VAL(vsync_srtr, vsync_wid) \ macro 395 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(1025,3); in radeon_setmode_9200() 428 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(769,3); in radeon_setmode_9200() 434 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(771,6) \| CRTC_V_SYNC_POL; in radeon_setmode_9200() 459 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,3); in radeon_setmode_9200() 464 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,4); in radeon_setmode_9200() 490 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(481,3) \| CRTC_V_SYNC_POL; in radeon_setmode_9200() 496 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(491,2) \| CRTC_V_SYNC_POL; in radeon_setmode_9200()
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot-sam460ex/drivers/video/
H A D	ati_radeon_fb.c	79 #define CRTC_VSYNC_STRT_WID_VAL(vsync_srtr, vsync_wid) \ macro 415 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(1025,3); in radeon_setmode_9200() 448 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(769,3); in radeon_setmode_9200() 454 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(771,6) \| CRTC_V_SYNC_POL; in radeon_setmode_9200() 479 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,3); in radeon_setmode_9200() 484 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,4); in radeon_setmode_9200() 510 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(481,3) \| CRTC_V_SYNC_POL; in radeon_setmode_9200() 516 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(491,2) \| CRTC_V_SYNC_POL; in radeon_setmode_9200()
/dports/sysutils/u-boot-nanopi-neo2/u-boot-2021.07/drivers/video/
H A D	ati_radeon_fb.c	59 #define CRTC_VSYNC_STRT_WID_VAL(vsync_srtr, vsync_wid) \ macro 395 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(1025,3); in radeon_setmode_9200() 428 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(769,3); in radeon_setmode_9200() 434 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(771,6) \| CRTC_V_SYNC_POL; in radeon_setmode_9200() 459 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,3); in radeon_setmode_9200() 464 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,4); in radeon_setmode_9200() 490 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(481,3) \| CRTC_V_SYNC_POL; in radeon_setmode_9200() 496 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(491,2) \| CRTC_V_SYNC_POL; in radeon_setmode_9200()
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/video/
H A D	ati_radeon_fb.c	59 #define CRTC_VSYNC_STRT_WID_VAL(vsync_srtr, vsync_wid) \ macro 395 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(1025,3); in radeon_setmode_9200() 428 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(769,3); in radeon_setmode_9200() 434 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(771,6) \| CRTC_V_SYNC_POL; in radeon_setmode_9200() 459 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,3); in radeon_setmode_9200() 464 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,4); in radeon_setmode_9200() 490 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(481,3) \| CRTC_V_SYNC_POL; in radeon_setmode_9200() 496 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(491,2) \| CRTC_V_SYNC_POL; in radeon_setmode_9200()
/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/video/
H A D	ati_radeon_fb.c	59 #define CRTC_VSYNC_STRT_WID_VAL(vsync_srtr, vsync_wid) \ macro 395 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(1025,3); in radeon_setmode_9200() 428 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(769,3); in radeon_setmode_9200() 434 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(771,6) \| CRTC_V_SYNC_POL; in radeon_setmode_9200() 459 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,3); in radeon_setmode_9200() 464 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,4); in radeon_setmode_9200() 490 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(481,3) \| CRTC_V_SYNC_POL; in radeon_setmode_9200() 496 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(491,2) \| CRTC_V_SYNC_POL; in radeon_setmode_9200()
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/video/
H A D	ati_radeon_fb.c	59 #define CRTC_VSYNC_STRT_WID_VAL(vsync_srtr, vsync_wid) \ macro 395 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(1025,3); in radeon_setmode_9200() 428 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(769,3); in radeon_setmode_9200() 434 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(771,6) \| CRTC_V_SYNC_POL; in radeon_setmode_9200() 459 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,3); in radeon_setmode_9200() 464 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,4); in radeon_setmode_9200() 490 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(481,3) \| CRTC_V_SYNC_POL; in radeon_setmode_9200() 496 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(491,2) \| CRTC_V_SYNC_POL; in radeon_setmode_9200()
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/drivers/video/
H A D	ati_radeon_fb.c	57 #define CRTC_VSYNC_STRT_WID_VAL(vsync_srtr, vsync_wid) \ macro 393 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(1025,3); in radeon_setmode_9200() 426 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(769,3); in radeon_setmode_9200() 432 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(771,6) \| CRTC_V_SYNC_POL; in radeon_setmode_9200() 457 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,3); in radeon_setmode_9200() 462 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,4); in radeon_setmode_9200() 488 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(481,3) \| CRTC_V_SYNC_POL; in radeon_setmode_9200() 494 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(491,2) \| CRTC_V_SYNC_POL; in radeon_setmode_9200()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/drivers/video/
H A D	ati_radeon_fb.c	57 #define CRTC_VSYNC_STRT_WID_VAL(vsync_srtr, vsync_wid) \ macro 393 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(1025,3); in radeon_setmode_9200() 426 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(769,3); in radeon_setmode_9200() 432 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(771,6) \| CRTC_V_SYNC_POL; in radeon_setmode_9200() 457 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,3); in radeon_setmode_9200() 462 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,4); in radeon_setmode_9200() 488 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(481,3) \| CRTC_V_SYNC_POL; in radeon_setmode_9200() 494 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(491,2) \| CRTC_V_SYNC_POL; in radeon_setmode_9200()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/drivers/video/
H A D	ati_radeon_fb.c	79 #define CRTC_VSYNC_STRT_WID_VAL(vsync_srtr, vsync_wid) \ macro 415 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(1025,3); in radeon_setmode_9200() 448 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(769,3); in radeon_setmode_9200() 454 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(771,6) \| CRTC_V_SYNC_POL; in radeon_setmode_9200() 479 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,3); in radeon_setmode_9200() 484 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,4); in radeon_setmode_9200() 510 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(481,3) \| CRTC_V_SYNC_POL; in radeon_setmode_9200() 516 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(491,2) \| CRTC_V_SYNC_POL; in radeon_setmode_9200()

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