| /dports/sysutils/atf-sun50i_h6/arm-trusted-firmware-2.5/plat/rockchip/rk3328/drivers/pmu/ |
| H A D | pmu.c | 195 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(CPLL_ID)); in rockchip_soc_soft_reset()
196 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(GPLL_ID)); in rockchip_soc_soft_reset()
197 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(NPLL_ID)); in rockchip_soc_soft_reset()
198 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(APLL_ID)); in rockchip_soc_soft_reset()
301 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(DPLL_ID)); in dpll_suspend()
336 mmio_write_32(CRU_BASE + CRU_CRU_MODE, in dpll_resume()
345 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(pll_id)); in pll_suspend()
364 mmio_write_32(CRU_BASE + CRU_CRU_MODE, in pll_resume()
370 ddr_data.cru_mode_save = mmio_read_32(CRU_BASE + CRU_CRU_MODE); in pm_plls_suspend()
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| /dports/sysutils/atf-sun50i_a64/arm-trusted-firmware-2.5/plat/rockchip/rk3328/drivers/pmu/ |
| H A D | pmu.c | 195 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(CPLL_ID)); in rockchip_soc_soft_reset()
196 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(GPLL_ID)); in rockchip_soc_soft_reset()
197 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(NPLL_ID)); in rockchip_soc_soft_reset()
198 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(APLL_ID)); in rockchip_soc_soft_reset()
301 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(DPLL_ID)); in dpll_suspend()
336 mmio_write_32(CRU_BASE + CRU_CRU_MODE, in dpll_resume()
345 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(pll_id)); in pll_suspend()
364 mmio_write_32(CRU_BASE + CRU_CRU_MODE, in pll_resume()
370 ddr_data.cru_mode_save = mmio_read_32(CRU_BASE + CRU_CRU_MODE); in pm_plls_suspend()
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| /dports/sysutils/atf-rk3399/arm-trusted-firmware-2.5/plat/rockchip/rk3328/drivers/pmu/ |
| H A D | pmu.c | 195 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(CPLL_ID)); in rockchip_soc_soft_reset()
196 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(GPLL_ID)); in rockchip_soc_soft_reset()
197 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(NPLL_ID)); in rockchip_soc_soft_reset()
198 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(APLL_ID)); in rockchip_soc_soft_reset()
301 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(DPLL_ID)); in dpll_suspend()
336 mmio_write_32(CRU_BASE + CRU_CRU_MODE, in dpll_resume()
345 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(pll_id)); in pll_suspend()
364 mmio_write_32(CRU_BASE + CRU_CRU_MODE, in pll_resume()
370 ddr_data.cru_mode_save = mmio_read_32(CRU_BASE + CRU_CRU_MODE); in pm_plls_suspend()
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| /dports/sysutils/atf-rk3328/arm-trusted-firmware-2.5/plat/rockchip/rk3328/drivers/pmu/ |
| H A D | pmu.c | 195 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(CPLL_ID)); in rockchip_soc_soft_reset()
196 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(GPLL_ID)); in rockchip_soc_soft_reset()
197 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(NPLL_ID)); in rockchip_soc_soft_reset()
198 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(APLL_ID)); in rockchip_soc_soft_reset()
301 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(DPLL_ID)); in dpll_suspend()
336 mmio_write_32(CRU_BASE + CRU_CRU_MODE, in dpll_resume()
345 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(pll_id)); in pll_suspend()
364 mmio_write_32(CRU_BASE + CRU_CRU_MODE, in pll_resume()
370 ddr_data.cru_mode_save = mmio_read_32(CRU_BASE + CRU_CRU_MODE); in pm_plls_suspend()
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| /dports/sysutils/atf-fvp/arm-trusted-firmware-2.5/plat/rockchip/rk3328/drivers/pmu/ |
| H A D | pmu.c | 195 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(CPLL_ID)); in rockchip_soc_soft_reset()
196 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(GPLL_ID)); in rockchip_soc_soft_reset()
197 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(NPLL_ID)); in rockchip_soc_soft_reset()
198 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(APLL_ID)); in rockchip_soc_soft_reset()
301 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(DPLL_ID)); in dpll_suspend()
336 mmio_write_32(CRU_BASE + CRU_CRU_MODE, in dpll_resume()
345 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(pll_id)); in pll_suspend()
364 mmio_write_32(CRU_BASE + CRU_CRU_MODE, in pll_resume()
370 ddr_data.cru_mode_save = mmio_read_32(CRU_BASE + CRU_CRU_MODE); in pm_plls_suspend()
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| /dports/sysutils/atf-sun50i_a64/arm-trusted-firmware-2.5/plat/rockchip/rk3328/drivers/soc/ |
| H A D | soc.h | 35 #define CRU_CRU_MODE 0x0080 macro
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| /dports/sysutils/atf-sun50i_h6/arm-trusted-firmware-2.5/plat/rockchip/rk3328/drivers/soc/ |
| H A D | soc.h | 35 #define CRU_CRU_MODE 0x0080 macro
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| /dports/sysutils/atf-rk3399/arm-trusted-firmware-2.5/plat/rockchip/rk3328/drivers/soc/ |
| H A D | soc.h | 35 #define CRU_CRU_MODE 0x0080 macro
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| /dports/sysutils/atf-rk3328/arm-trusted-firmware-2.5/plat/rockchip/rk3328/drivers/soc/ |
| H A D | soc.h | 35 #define CRU_CRU_MODE 0x0080 macro
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| /dports/sysutils/atf-fvp/arm-trusted-firmware-2.5/plat/rockchip/rk3328/drivers/soc/ |
| H A D | soc.h | 35 #define CRU_CRU_MODE 0x0080 macro
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