/dports/sysutils/uefi-edk2-bhyve-csm/uefi-edk2-aa8d718/Vlv2TbltDevicePkg/Override/MdeModulePkg/Bus/Pci/XhciDxe/ |
H A D | XhciReg.c | 109 ASSERT (Xhc->CapLength != 0); in XhcReadOpReg() 115 (UINT64) (Xhc->CapLength + Offset), in XhcReadOpReg() 145 ASSERT (Xhc->CapLength != 0); in XhcWriteOpReg() 151 (UINT64) (Xhc->CapLength + Offset), in XhcWriteOpReg() 178 ASSERT (Xhc->CapLength != 0); in XhcWriteOpReg16() 184 (UINT64) (Xhc->CapLength + Offset), in XhcWriteOpReg16()
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/dports/sysutils/uefi-edk2-bhyve-csm/uefi-edk2-aa8d718/MdeModulePkg/Bus/Pci/XhciDxe/ |
H A D | XhciReg.c | 109 ASSERT (Xhc->CapLength != 0); in XhcReadOpReg() 115 (UINT64) (Xhc->CapLength + Offset), in XhcReadOpReg() 145 ASSERT (Xhc->CapLength != 0); in XhcWriteOpReg() 151 (UINT64) (Xhc->CapLength + Offset), in XhcWriteOpReg() 178 ASSERT (Xhc->CapLength != 0); in XhcWriteOpReg16() 184 (UINT64) (Xhc->CapLength + Offset), in XhcWriteOpReg16()
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/dports/emulators/qemu60/qemu-6.0.0/roms/edk2/MdeModulePkg/Bus/Pci/XhciDxe/ |
H A D | XhciReg.c | 103 ASSERT (Xhc->CapLength != 0); in XhcReadOpReg() 109 Xhc->CapLength + Offset, in XhcReadOpReg() 139 ASSERT (Xhc->CapLength != 0); in XhcWriteOpReg() 145 Xhc->CapLength + Offset, in XhcWriteOpReg()
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/dports/sysutils/uefi-edk2-bhyve/edk2-edk2-stable202102/MdeModulePkg/Bus/Pci/XhciDxe/ |
H A D | XhciReg.c | 103 ASSERT (Xhc->CapLength != 0); in XhcReadOpReg() 109 Xhc->CapLength + Offset, in XhcReadOpReg() 139 ASSERT (Xhc->CapLength != 0); in XhcWriteOpReg() 145 Xhc->CapLength + Offset, in XhcWriteOpReg()
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/dports/emulators/qemu42/qemu-4.2.1/roms/edk2/MdeModulePkg/Bus/Pci/XhciDxe/ |
H A D | XhciReg.c | 103 ASSERT (Xhc->CapLength != 0); in XhcReadOpReg() 109 Xhc->CapLength + Offset, in XhcReadOpReg() 139 ASSERT (Xhc->CapLength != 0); in XhcWriteOpReg() 145 Xhc->CapLength + Offset, in XhcWriteOpReg()
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/dports/emulators/qemu/qemu-6.2.0/roms/edk2/MdeModulePkg/Bus/Pci/XhciDxe/ |
H A D | XhciReg.c | 103 ASSERT (Xhc->CapLength != 0); in XhcReadOpReg() 109 Xhc->CapLength + Offset, in XhcReadOpReg() 139 ASSERT (Xhc->CapLength != 0); in XhcWriteOpReg() 145 Xhc->CapLength + Offset, in XhcWriteOpReg()
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/dports/emulators/qemu5/qemu-5.2.0/roms/edk2/MdeModulePkg/Bus/Pci/XhciDxe/ |
H A D | XhciReg.c | 103 ASSERT (Xhc->CapLength != 0); in XhcReadOpReg() 109 Xhc->CapLength + Offset, in XhcReadOpReg() 139 ASSERT (Xhc->CapLength != 0); in XhcWriteOpReg() 145 Xhc->CapLength + Offset, in XhcWriteOpReg()
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/dports/sysutils/uefi-edk2-qemu/edk2-edk2-stable201911/MdeModulePkg/Bus/Pci/XhciDxe/ |
H A D | XhciReg.c | 103 ASSERT (Xhc->CapLength != 0); in XhcReadOpReg() 109 Xhc->CapLength + Offset, in XhcReadOpReg() 139 ASSERT (Xhc->CapLength != 0); in XhcWriteOpReg() 145 Xhc->CapLength + Offset, in XhcWriteOpReg()
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/dports/emulators/qemu-utils/qemu-4.2.1/roms/edk2/MdeModulePkg/Bus/Pci/XhciDxe/ |
H A D | XhciReg.c | 103 ASSERT (Xhc->CapLength != 0); in XhcReadOpReg() 109 Xhc->CapLength + Offset, in XhcReadOpReg() 139 ASSERT (Xhc->CapLength != 0); in XhcWriteOpReg() 145 Xhc->CapLength + Offset, in XhcWriteOpReg()
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/edk2/MdeModulePkg/Bus/Pci/XhciDxe/ |
H A D | XhciReg.c | 103 ASSERT (Xhc->CapLength != 0); in XhcReadOpReg() 109 Xhc->CapLength + Offset, in XhcReadOpReg() 139 ASSERT (Xhc->CapLength != 0); in XhcWriteOpReg() 145 Xhc->CapLength + Offset, in XhcWriteOpReg()
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/dports/sysutils/edk2/edk2-edk2-stable202102/MdeModulePkg/Bus/Pci/XhciDxe/ |
H A D | XhciReg.c | 103 ASSERT (Xhc->CapLength != 0); 109 Xhc->CapLength + Offset, 139 ASSERT (Xhc->CapLength != 0); 145 Xhc->CapLength + Offset, in setup_parser_errposition_callback()
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/dports/sysutils/uefi-edk2-bhyve-csm/uefi-edk2-aa8d718/MdeModulePkg/Bus/Pci/XhciPei/ |
H A D | XhcPeim.c | 86 ASSERT (Xhc->CapLength != 0); in XhcPeiReadOpReg() 88 Data = MmioRead32 (Xhc->UsbHostControllerBaseAddress + Xhc->CapLength + Offset); in XhcPeiReadOpReg() 107 ASSERT (Xhc->CapLength != 0); in XhcPeiWriteOpReg() 109 MmioWrite32 (Xhc->UsbHostControllerBaseAddress + Xhc->CapLength + Offset, Data); in XhcPeiWriteOpReg() 1453 …XhcDev->CapLength = (UINT8) (XhcPeiReadCapRegister (XhcDev, XHC_CAPLENGTH_OFFSET) & 0x0F… in XhcPeimEntry() 1469 DEBUG ((EFI_D_INFO, "XhciPei: CapLength: %x\n", XhcDev->CapLength)); in XhcPeimEntry()
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H A D | XhcPeim.h | 153 UINT8 CapLength; ///< Capability Register Length member
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/dports/emulators/qemu42/qemu-4.2.1/roms/edk2/MdeModulePkg/Bus/Pci/XhciPei/ |
H A D | XhcPeim.c | 79 ASSERT (Xhc->CapLength != 0); in XhcPeiReadOpReg() 81 Data = MmioRead32 (Xhc->UsbHostControllerBaseAddress + Xhc->CapLength + Offset); in XhcPeiReadOpReg() 100 ASSERT (Xhc->CapLength != 0); in XhcPeiWriteOpReg() 102 MmioWrite32 (Xhc->UsbHostControllerBaseAddress + Xhc->CapLength + Offset, Data); in XhcPeiWriteOpReg() 1489 …XhcDev->CapLength = (UINT8) (XhcPeiReadCapRegister (XhcDev, XHC_CAPLENGTH_OFFSET) & 0x0F… in XhcPeimEntry() 1505 DEBUG ((EFI_D_INFO, "XhciPei: CapLength: %x\n", XhcDev->CapLength)); in XhcPeimEntry()
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H A D | XhcPeim.h | 159 UINT8 CapLength; ///< Capability Register Length member
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/dports/emulators/qemu/qemu-6.2.0/roms/edk2/MdeModulePkg/Bus/Pci/XhciPei/ |
H A D | XhcPeim.c | 79 ASSERT (Xhc->CapLength != 0); in XhcPeiReadOpReg() 81 Data = MmioRead32 (Xhc->UsbHostControllerBaseAddress + Xhc->CapLength + Offset); in XhcPeiReadOpReg() 100 ASSERT (Xhc->CapLength != 0); in XhcPeiWriteOpReg() 102 MmioWrite32 (Xhc->UsbHostControllerBaseAddress + Xhc->CapLength + Offset, Data); in XhcPeiWriteOpReg() 1489 …XhcDev->CapLength = (UINT8) (XhcPeiReadCapRegister (XhcDev, XHC_CAPLENGTH_OFFSET) & 0x0F… in XhcPeimEntry() 1505 DEBUG ((EFI_D_INFO, "XhciPei: CapLength: %x\n", XhcDev->CapLength)); in XhcPeimEntry()
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/dports/emulators/qemu5/qemu-5.2.0/roms/edk2/MdeModulePkg/Bus/Pci/XhciPei/ |
H A D | XhcPeim.c | 79 ASSERT (Xhc->CapLength != 0); in XhcPeiReadOpReg() 81 Data = MmioRead32 (Xhc->UsbHostControllerBaseAddress + Xhc->CapLength + Offset); in XhcPeiReadOpReg() 100 ASSERT (Xhc->CapLength != 0); in XhcPeiWriteOpReg() 102 MmioWrite32 (Xhc->UsbHostControllerBaseAddress + Xhc->CapLength + Offset, Data); in XhcPeiWriteOpReg() 1489 …XhcDev->CapLength = (UINT8) (XhcPeiReadCapRegister (XhcDev, XHC_CAPLENGTH_OFFSET) & 0x0F… in XhcPeimEntry() 1505 DEBUG ((EFI_D_INFO, "XhciPei: CapLength: %x\n", XhcDev->CapLength)); in XhcPeimEntry()
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/dports/emulators/qemu60/qemu-6.0.0/roms/edk2/MdeModulePkg/Bus/Pci/XhciPei/ |
H A D | XhcPeim.c | 79 ASSERT (Xhc->CapLength != 0); in XhcPeiReadOpReg() 81 Data = MmioRead32 (Xhc->UsbHostControllerBaseAddress + Xhc->CapLength + Offset); in XhcPeiReadOpReg() 100 ASSERT (Xhc->CapLength != 0); in XhcPeiWriteOpReg() 102 MmioWrite32 (Xhc->UsbHostControllerBaseAddress + Xhc->CapLength + Offset, Data); in XhcPeiWriteOpReg() 1489 …XhcDev->CapLength = (UINT8) (XhcPeiReadCapRegister (XhcDev, XHC_CAPLENGTH_OFFSET) & 0x0F… in XhcPeimEntry() 1505 DEBUG ((EFI_D_INFO, "XhciPei: CapLength: %x\n", XhcDev->CapLength)); in XhcPeimEntry()
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/dports/emulators/qemu-utils/qemu-4.2.1/roms/edk2/MdeModulePkg/Bus/Pci/XhciPei/ |
H A D | XhcPeim.c | 79 ASSERT (Xhc->CapLength != 0); in XhcPeiReadOpReg() 81 Data = MmioRead32 (Xhc->UsbHostControllerBaseAddress + Xhc->CapLength + Offset); in XhcPeiReadOpReg() 100 ASSERT (Xhc->CapLength != 0); in XhcPeiWriteOpReg() 102 MmioWrite32 (Xhc->UsbHostControllerBaseAddress + Xhc->CapLength + Offset, Data); in XhcPeiWriteOpReg() 1489 …XhcDev->CapLength = (UINT8) (XhcPeiReadCapRegister (XhcDev, XHC_CAPLENGTH_OFFSET) & 0x0F… in XhcPeimEntry() 1505 DEBUG ((EFI_D_INFO, "XhciPei: CapLength: %x\n", XhcDev->CapLength)); in XhcPeimEntry()
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H A D | XhcPeim.h | 159 UINT8 CapLength; ///< Capability Register Length member
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/dports/sysutils/uefi-edk2-qemu/edk2-edk2-stable201911/MdeModulePkg/Bus/Pci/XhciPei/ |
H A D | XhcPeim.c | 79 ASSERT (Xhc->CapLength != 0); in XhcPeiReadOpReg() 81 Data = MmioRead32 (Xhc->UsbHostControllerBaseAddress + Xhc->CapLength + Offset); in XhcPeiReadOpReg() 100 ASSERT (Xhc->CapLength != 0); in XhcPeiWriteOpReg() 102 MmioWrite32 (Xhc->UsbHostControllerBaseAddress + Xhc->CapLength + Offset, Data); in XhcPeiWriteOpReg() 1489 …XhcDev->CapLength = (UINT8) (XhcPeiReadCapRegister (XhcDev, XHC_CAPLENGTH_OFFSET) & 0x0F… in XhcPeimEntry() 1505 DEBUG ((EFI_D_INFO, "XhciPei: CapLength: %x\n", XhcDev->CapLength)); in XhcPeimEntry()
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/dports/sysutils/uefi-edk2-bhyve/edk2-edk2-stable202102/MdeModulePkg/Bus/Pci/XhciPei/ |
H A D | XhcPeim.c | 79 ASSERT (Xhc->CapLength != 0); in XhcPeiReadOpReg() 81 Data = MmioRead32 (Xhc->UsbHostControllerBaseAddress + Xhc->CapLength + Offset); in XhcPeiReadOpReg() 100 ASSERT (Xhc->CapLength != 0); in XhcPeiWriteOpReg() 102 MmioWrite32 (Xhc->UsbHostControllerBaseAddress + Xhc->CapLength + Offset, Data); in XhcPeiWriteOpReg() 1489 …XhcDev->CapLength = (UINT8) (XhcPeiReadCapRegister (XhcDev, XHC_CAPLENGTH_OFFSET) & 0x0F… in XhcPeimEntry() 1505 DEBUG ((EFI_D_INFO, "XhciPei: CapLength: %x\n", XhcDev->CapLength)); in XhcPeimEntry()
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/edk2/MdeModulePkg/Bus/Pci/XhciPei/ |
H A D | XhcPeim.c | 79 ASSERT (Xhc->CapLength != 0); in XhcPeiReadOpReg() 81 Data = MmioRead32 (Xhc->UsbHostControllerBaseAddress + Xhc->CapLength + Offset); in XhcPeiReadOpReg() 100 ASSERT (Xhc->CapLength != 0); in XhcPeiWriteOpReg() 102 MmioWrite32 (Xhc->UsbHostControllerBaseAddress + Xhc->CapLength + Offset, Data); in XhcPeiWriteOpReg() 1489 …XhcDev->CapLength = (UINT8) (XhcPeiReadCapRegister (XhcDev, XHC_CAPLENGTH_OFFSET) & 0x0F… in XhcPeimEntry() 1505 DEBUG ((EFI_D_INFO, "XhciPei: CapLength: %x\n", XhcDev->CapLength)); in XhcPeimEntry()
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/dports/sysutils/edk2/edk2-edk2-stable202102/MdeModulePkg/Bus/Pci/XhciPei/ |
H A D | XhcPeim.c | 79 ASSERT (Xhc->CapLength != 0); in XhcPeiReadOpReg() 81 Data = MmioRead32 (Xhc->UsbHostControllerBaseAddress + Xhc->CapLength + Offset); in XhcPeiReadOpReg() 100 ASSERT (Xhc->CapLength != 0); in XhcPeiWriteOpReg() 102 MmioWrite32 (Xhc->UsbHostControllerBaseAddress + Xhc->CapLength + Offset, Data); in XhcPeiWriteOpReg() 1489 …XhcDev->CapLength = (UINT8) (XhcPeiReadCapRegister (XhcDev, XHC_CAPLENGTH_OFFSET) & 0x0F… in XhcPeimEntry() 1505 DEBUG ((EFI_D_INFO, "XhciPei: CapLength: %x\n", XhcDev->CapLength)); in XhcPeimEntry()
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/dports/sysutils/edk2/edk2-platforms-89f6170d/Features/Intel/Debugging/Usb3DebugFeaturePkg/Library/Usb3DebugPortLib/ |
H A D | Usb3DebugPortInitialize.c | 172 UINT8 CapLength; in DiscoverUsb3DebugPort() local 214 CapLength = MmioRead8 ((UINTN) UsbBase); in DiscoverUsb3DebugPort() 248 Instance->XhciOpRegister = UsbBase + CapLength; in DiscoverUsb3DebugPort()
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