Home
last modified time | relevance | path

Searched refs:Clk (Results 1 – 25 of 468) sorted by relevance

12345678910>>...19

/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/simple_gemac/miim/
H A Deth_miim.v100 Clk,
209 always @ (posedge Clk or posedge Reset)
225 always @ (posedge Clk or posedge Reset)
239 always @ (posedge Clk or posedge Reset)
274 always @ (posedge Clk or posedge Reset)
302 always @ (posedge Clk or posedge Reset)
321 always @ (posedge Clk or posedge Reset)
372 always @ (posedge Clk or posedge Reset)
385 always @ (posedge Clk or posedge Reset)
459 eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad…
[all …]
H A Deth_clockgen.v81 module eth_clockgen(Clk, Reset, Divider, MdcEn, MdcEn_n, Mdc);
85 input Clk; // Input clock (Host clock) port
106 always @ (posedge Clk or posedge Reset)
123 always @ (posedge Clk or posedge Reset)
H A Deth_outputcontrol.v84 module eth_outputcontrol(Clk, Reset, InProgress, ShiftedBit, BitCounter, WriteOp, NoPre, MdcEn_n, M…
86 input Clk; // Host Clock port
116 always @ (posedge Clk or posedge Reset)
137 always @ (posedge Clk or posedge Reset)
H A Deth_shiftreg.v87 module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect,
91 input Clk; // Input clock (Host clock) port
114 always @ (posedge Clk or posedge Reset)
/dports/cad/ghdl/ghdl-1.0.0/testsuite/gna/issue17/
H A Dcond_assign_proc.vhdl8 signal Clk : std_logic := '0' ; signal
11 Clk <= not Clk after 10 ns ;
13 process (Clk)
16 A := 'H' when Clk = '1' else 'L' ;
18 -- Y <= 'H' when Clk = '1' else 'L' ;
21 -- Y <= 'H' when Clk = '1' else 'L' ;
H A Dcond_assign_var.vhdl9 signal Clk : std_logic := '0' ; signal
12 Clk <= not Clk after 10 ns ;
14 process (Clk)
17 A := 'H' when Clk = '1' else 'L' ;
19 -- Y <= 'H' when Clk = '1' else 'L' ;
22 -- Y <= 'H' when Clk = '1' else 'L' ;
H A Dcond_assign_sig.vhdl9 signal Clk : std_logic := '0' ; signal
12 Clk <= not Clk after 10 ns ;
14 process (Clk)
16 Y <= 'H' when Clk = '1' else 'L' ;
19 -- Y <= 'H' when Clk = '1' else 'L' ;
/dports/cad/ghdl/ghdl-1.0.0/src/synth/
H A Dnetlists-inference.adb276 Clk := No_Net;
281 Clk := N;
296 Clk := I0;
331 Clk : Net;
489 Clk : Net;
805 Clk : Net; variable
862 if Clk = No_Net then
871 Clk, Enable, Stmt);
924 Clk, En : Net; variable
942 exit when Clk /= No_Net;
[all …]
H A Dnetlists-memories.adb517 Clk := No_Net;
531 Clk, En : Net; variable
570 if Clk = No_Net then
613 Clk, En : Net; variable
712 if Clk = No_Net then
1018 Clk : Net; variable
1931 Clk : Net; variable
1949 if Clk /= No_Net then
2032 Clk : Net; variable
2551 En := Clk;
[all …]
H A Dnetlists-builders.ads150 Clk : Net;
156 Clk : Net;
187 Clk : Net;
192 Clk : Net;
196 Clk : Net;
199 Clk : Net;
204 Clk : Net;
208 Clk : Net;
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/dboards/common/sync/
H A DPulser.vhd48 Clk : in std_logic; port
87 CheckInputRanges : process(Clk)
89 if falling_edge(Clk) then
120 elsif rising_edge(Clk) then
180 signal Clk: std_logic := '0'; signal
203 Clk <= not Clk after kPer/2 when not StopSim else '0';
226 wait until falling_edge(Clk);
232 wait until falling_edge(Clk);
266 wait until falling_edge(Clk);
317 Clk => Clk, --in std_logic
[all …]
/dports/cad/ghdl/ghdl-1.0.0/testsuite/gna/issue375/
H A Dcond_assign_proc.vhdl9 signal Clk : std_logic := '0' ; signal
12 Clk <= not Clk after 10 ns ;
16 Y <= '1' when Clk = '1' else '0' ;
/dports/cad/ghdl/ghdl-1.0.0/testsuite/gna/ticket104/
H A Dbug_tb.vhd16 signal Clk : std_logic := '1'; signal
29 Clk <= not Clk after 10 ns;
34 wait until rising_edge(Clk);
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/video/fbdev/via/
H A Dvt1636.c140 static int get_clk_range_index(u32 Clk) in get_clk_range_index() argument
142 if (Clk < DPA_CLK_30M) in get_clk_range_index()
144 else if (Clk < DPA_CLK_50M) in get_clk_range_index()
146 else if (Clk < DPA_CLK_70M) in get_clk_range_index()
148 else if (Clk < DPA_CLK_100M) in get_clk_range_index()
150 else if (Clk < DPA_CLK_150M) in get_clk_range_index()
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/video/fbdev/via/
H A Dvt1636.c140 static int get_clk_range_index(u32 Clk) in get_clk_range_index() argument
142 if (Clk < DPA_CLK_30M) in get_clk_range_index()
144 else if (Clk < DPA_CLK_50M) in get_clk_range_index()
146 else if (Clk < DPA_CLK_70M) in get_clk_range_index()
148 else if (Clk < DPA_CLK_100M) in get_clk_range_index()
150 else if (Clk < DPA_CLK_150M) in get_clk_range_index()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/video/fbdev/via/
H A Dvt1636.c140 static int get_clk_range_index(u32 Clk) in get_clk_range_index() argument
142 if (Clk < DPA_CLK_30M) in get_clk_range_index()
144 else if (Clk < DPA_CLK_50M) in get_clk_range_index()
146 else if (Clk < DPA_CLK_70M) in get_clk_range_index()
148 else if (Clk < DPA_CLK_100M) in get_clk_range_index()
150 else if (Clk < DPA_CLK_150M) in get_clk_range_index()
/dports/cad/verilator/verilator-4.216/test_regress/t/
H A Dt_mem_slot.v9 module t_mem_slot (Clk, SlotIdx, BitToChange, BitVal, SlotToReturn, OutputVal);
11 input Clk; port
20 always @(posedge Clk)
/dports/cad/ghdl/ghdl-1.0.0/testsuite/gna/issue1051/
H A Dpsi_tb_activity_pkg.vhd52 signal Clk : in std_logic);
61 signal Clk : in std_logic);
65 signal Clk : in std_logic);
164 signal Clk : in std_logic) is
166 wait until rising_edge(Clk);
168 wait until rising_edge(Clk);
177 wait until rising_edge(Clk) and Sig = Val;
182 signal Clk : in std_logic) is
185 wait until rising_edge(Clk);
191 signal Clk : in std_logic) is
[all …]
H A Dpsi_common_i2c_master_tb.vhd62 signal Clk : std_logic := '1'; signal
104 wait until rising_edge(Clk);
157 Clk => Clk,
212 Clk <= not Clk;
225 wait until rising_edge(Clk);
226 wait until rising_edge(Clk);
241 wait until rising_edge(Clk);
253 wait until rising_edge(Clk);
266 wait until rising_edge(Clk);
292 wait until rising_edge(Clk);
[all …]
/dports/cad/pcb/pcb-4.2.0/lib/
H A DTTL_74xx_DIL.m4305 define(`PinList_7473_dil', ``1Clk',`/1Clr',`1K',`Vcc',`2Clk',`/2Clr',`2J',`/2Q',`2Q',`2K',`Gnd',`1Q…
310 define(`PinList_7474_dil', ``/1Clr',`1D',`1Clk',`/1Pre',`1Q',`/1Q',`Gnd',`/2Q',`2Q',`/2Pre',`2Clk',…
320 define(`PinList_7476_dil', ``1Clk',`/1Pre',`/1Clr',`1J',`Vcc',`2Clk',`/2Pre',`/2Clr',`2J',`/2Q',`2Q…
380 define(`PinList_74107_dil', ``1J',`/1Q',`1Q',`1K',`2Q',`/2Q',`Gnd',`2J',`2Clk',`/2Clr',`2K',`1Clk',…
385 …efine(`PinList_74109_dil', ``/1Clr',`1J',`/1K',`1Clk',`/1Pre',`1Q',`/1Q',`Gnd',`/2Q',`2Q',`/2Pre',…
390 define(`PinList_74111_dil', ``1K',`/1Pre',`/1Clr',`1J',`1Clk',`/1Q',`1Q',`Gnd',`2Q',`/2Q',`2Clk',`2…
395 define(`PinList_74112_dil', ``1Clk',`1K',`1J',`/1Pre',`1Q',`/1Q',`/2Q',`Gnd',`2Q',`/2Pre',`2J',`2K'…
400 define(`PinList_74113_dil', ``1Clk',`1K',`1J',`/1Pre',`1Q',`/1Q',`Gnd',`/2Q',`2Q',`/2Pre',`2J',`2K'…
820 …ist_74276_dil', ``/Clr',`1J',`1Clk',`/1K',`1Q',`2Q',`/2K',`2Clk',`2J',`Gnd',`/Pre',`3J',`3Clk',`/3…
1025 define(`PinList_74393_dil', ``1Clk',`1Clr',`1Qa',`1Qb',`1Qc',`1Qd',`Gnd',`2Qd',`2Qc',`2Qb',`2Qa',`2…
[all …]
/dports/x11/eaglemode/eaglemode-0.95.0/src/emMain/
H A DemMainWindow.cpp349 Clk(0) in StartupEngineClass()
430 Clk=emGetClockMS(); in Cycle()
434 if (emGetClockMS()<Clk+2000 && VisitingVA->IsActive()) { in Cycle()
452 Clk=emGetClockMS(); in Cycle()
456 if (emGetClockMS()<Clk+2000 && VisitingVA->IsActive()) { in Cycle()
464 Clk=emGetClockMS(); in Cycle()
468 if (emGetClockMS()<Clk+100) { in Cycle()
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b200/
H A Dtiming.ucf23 INST "SFDX*" TNM = radio_misc_out; # Radio Clk domain
24 INST "SRX*" TNM = radio_misc_out; # Radio Clk domain
25 INST "LED_*" TNM = radio_misc_out; # Radio Clk domain
26 INST "tx_enable*" TNM = radio_misc_out; # Radio Clk domain
/dports/cad/yosys/yosys-yosys-0.12/tests/asicworld/
H A Dcode_hdl_models_GrayCounter.v15 input wire Clk); port
22 always @ (posedge Clk)
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Marvell/Drivers/SdMmc/XenonDxe/
H A DXenonSdhci.c136 UINT32 Clk; in XenonSetClk() local
168 Clk = (Div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; in XenonSetClk()
169 Clk |= ((Div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) << SDHCI_DIVIDER_HI_SHIFT; in XenonSetClk()
170 Clk |= SDHCI_CLOCK_INT_EN; in XenonSetClk()
172 XenonHcRwMmio (PciIo, SD_BAR_INDEX, SDHC_CLOCK_CTRL, FALSE, SDHC_REG_SIZE_2B, &Clk); in XenonSetClk()
181 XenonHcRwMmio (PciIo, SD_BAR_INDEX, SDHC_CLOCK_CTRL, TRUE, SDHC_REG_SIZE_2B, &Clk); in XenonSetClk()
192 } while (!(Clk & SDHCI_CLOCK_INT_STABLE)); in XenonSetClk()
194 Clk |= SDHCI_CLOCK_CARD_EN; in XenonSetClk()
195 XenonHcRwMmio (PciIo, SD_BAR_INDEX, SDHC_CLOCK_CTRL, FALSE, SDHC_REG_SIZE_2B, &Clk); in XenonSetClk()
/dports/cad/ghdl/ghdl-1.0.0/src/vhdl/
H A Dvhdl-sem_psl.adb678 Clk := Null_PSL_Node;
681 Clk := Get_Boolean (Prop);
684 Clk := Get_Boolean (Prop);
707 Clk : PSL_Node; variable
736 Extract_Clock (Prop, Clk);
738 Set_Global_Clock (Decl, Clk);
885 Clk : PSL_Node; variable
887 Extract_Clock (Prop, Clk);
888 if Clk = Null_PSL_Node then
891 Clk := Null_PSL_Node;
[all …]

12345678910>>...19