| /dports/devel/llvm70/llvm-7.0.1.src/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 1735 unsigned CombineOpc = 0;
1737 case ISD::VECREDUCE_FADD: CombineOpc = ISD::FADD; break;
1738 case ISD::VECREDUCE_FMUL: CombineOpc = ISD::FMUL; break;
1739 case ISD::VECREDUCE_ADD: CombineOpc = ISD::ADD; break;
1740 case ISD::VECREDUCE_MUL: CombineOpc = ISD::MUL; break;
1741 case ISD::VECREDUCE_AND: CombineOpc = ISD::AND; break;
1742 case ISD::VECREDUCE_OR: CombineOpc = ISD::OR; break;
1743 case ISD::VECREDUCE_XOR: CombineOpc = ISD::XOR; break;
1744 case ISD::VECREDUCE_SMAX: CombineOpc = ISD::SMAX; break;
1749 CombineOpc = NoNaN ? ISD::FMAXNUM : ISD::FMAXNAN;
[all …]
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| /dports/devel/llvm80/llvm-8.0.1.src/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 1832 unsigned CombineOpc = 0; in SplitVecOp_VECREDUCE() local
1834 case ISD::VECREDUCE_FADD: CombineOpc = ISD::FADD; break; in SplitVecOp_VECREDUCE()
1835 case ISD::VECREDUCE_FMUL: CombineOpc = ISD::FMUL; break; in SplitVecOp_VECREDUCE()
1836 case ISD::VECREDUCE_ADD: CombineOpc = ISD::ADD; break; in SplitVecOp_VECREDUCE()
1837 case ISD::VECREDUCE_MUL: CombineOpc = ISD::MUL; break; in SplitVecOp_VECREDUCE()
1838 case ISD::VECREDUCE_AND: CombineOpc = ISD::AND; break; in SplitVecOp_VECREDUCE()
1839 case ISD::VECREDUCE_OR: CombineOpc = ISD::OR; break; in SplitVecOp_VECREDUCE()
1840 case ISD::VECREDUCE_XOR: CombineOpc = ISD::XOR; break; in SplitVecOp_VECREDUCE()
1841 case ISD::VECREDUCE_SMAX: CombineOpc = ISD::SMAX; break; in SplitVecOp_VECREDUCE()
1846 CombineOpc = NoNaN ? ISD::FMAXNUM : ISD::FMAXIMUM; in SplitVecOp_VECREDUCE()
[all …]
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 2116 unsigned CombineOpc = 0; in SplitVecOp_VECREDUCE() local
2118 case ISD::VECREDUCE_FADD: CombineOpc = ISD::FADD; break; in SplitVecOp_VECREDUCE()
2119 case ISD::VECREDUCE_FMUL: CombineOpc = ISD::FMUL; break; in SplitVecOp_VECREDUCE()
2120 case ISD::VECREDUCE_ADD: CombineOpc = ISD::ADD; break; in SplitVecOp_VECREDUCE()
2121 case ISD::VECREDUCE_MUL: CombineOpc = ISD::MUL; break; in SplitVecOp_VECREDUCE()
2122 case ISD::VECREDUCE_AND: CombineOpc = ISD::AND; break; in SplitVecOp_VECREDUCE()
2123 case ISD::VECREDUCE_OR: CombineOpc = ISD::OR; break; in SplitVecOp_VECREDUCE()
2124 case ISD::VECREDUCE_XOR: CombineOpc = ISD::XOR; break; in SplitVecOp_VECREDUCE()
2125 case ISD::VECREDUCE_SMAX: CombineOpc = ISD::SMAX; break; in SplitVecOp_VECREDUCE()
2130 CombineOpc = NoNaN ? ISD::FMAXNUM : ISD::FMAXIMUM; in SplitVecOp_VECREDUCE()
[all …]
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| /dports/devel/llvm10/llvm-10.0.1.src/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 2068 unsigned CombineOpc = 0; in SplitVecOp_VECREDUCE() local
2070 case ISD::VECREDUCE_FADD: CombineOpc = ISD::FADD; break; in SplitVecOp_VECREDUCE()
2071 case ISD::VECREDUCE_FMUL: CombineOpc = ISD::FMUL; break; in SplitVecOp_VECREDUCE()
2072 case ISD::VECREDUCE_ADD: CombineOpc = ISD::ADD; break; in SplitVecOp_VECREDUCE()
2073 case ISD::VECREDUCE_MUL: CombineOpc = ISD::MUL; break; in SplitVecOp_VECREDUCE()
2074 case ISD::VECREDUCE_AND: CombineOpc = ISD::AND; break; in SplitVecOp_VECREDUCE()
2075 case ISD::VECREDUCE_OR: CombineOpc = ISD::OR; break; in SplitVecOp_VECREDUCE()
2076 case ISD::VECREDUCE_XOR: CombineOpc = ISD::XOR; break; in SplitVecOp_VECREDUCE()
2077 case ISD::VECREDUCE_SMAX: CombineOpc = ISD::SMAX; break; in SplitVecOp_VECREDUCE()
2082 CombineOpc = NoNaN ? ISD::FMAXNUM : ISD::FMAXIMUM; in SplitVecOp_VECREDUCE()
[all …]
|
| /dports/devel/llvm11/llvm-11.0.1.src/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 2116 unsigned CombineOpc = 0; in SplitVecOp_VECREDUCE() local
2118 case ISD::VECREDUCE_FADD: CombineOpc = ISD::FADD; break; in SplitVecOp_VECREDUCE()
2119 case ISD::VECREDUCE_FMUL: CombineOpc = ISD::FMUL; break; in SplitVecOp_VECREDUCE()
2120 case ISD::VECREDUCE_ADD: CombineOpc = ISD::ADD; break; in SplitVecOp_VECREDUCE()
2121 case ISD::VECREDUCE_MUL: CombineOpc = ISD::MUL; break; in SplitVecOp_VECREDUCE()
2122 case ISD::VECREDUCE_AND: CombineOpc = ISD::AND; break; in SplitVecOp_VECREDUCE()
2123 case ISD::VECREDUCE_OR: CombineOpc = ISD::OR; break; in SplitVecOp_VECREDUCE()
2124 case ISD::VECREDUCE_XOR: CombineOpc = ISD::XOR; break; in SplitVecOp_VECREDUCE()
2125 case ISD::VECREDUCE_SMAX: CombineOpc = ISD::SMAX; break; in SplitVecOp_VECREDUCE()
2130 CombineOpc = NoNaN ? ISD::FMAXNUM : ISD::FMAXIMUM; in SplitVecOp_VECREDUCE()
[all …]
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| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 2068 unsigned CombineOpc = 0; in SplitVecOp_VECREDUCE() local
2070 case ISD::VECREDUCE_FADD: CombineOpc = ISD::FADD; break; in SplitVecOp_VECREDUCE()
2071 case ISD::VECREDUCE_FMUL: CombineOpc = ISD::FMUL; break; in SplitVecOp_VECREDUCE()
2072 case ISD::VECREDUCE_ADD: CombineOpc = ISD::ADD; break; in SplitVecOp_VECREDUCE()
2073 case ISD::VECREDUCE_MUL: CombineOpc = ISD::MUL; break; in SplitVecOp_VECREDUCE()
2074 case ISD::VECREDUCE_AND: CombineOpc = ISD::AND; break; in SplitVecOp_VECREDUCE()
2075 case ISD::VECREDUCE_OR: CombineOpc = ISD::OR; break; in SplitVecOp_VECREDUCE()
2076 case ISD::VECREDUCE_XOR: CombineOpc = ISD::XOR; break; in SplitVecOp_VECREDUCE()
2077 case ISD::VECREDUCE_SMAX: CombineOpc = ISD::SMAX; break; in SplitVecOp_VECREDUCE()
2082 CombineOpc = NoNaN ? ISD::FMAXNUM : ISD::FMAXIMUM; in SplitVecOp_VECREDUCE()
[all …]
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| /dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 2068 unsigned CombineOpc = 0; in SplitVecOp_VECREDUCE() local
2070 case ISD::VECREDUCE_FADD: CombineOpc = ISD::FADD; break; in SplitVecOp_VECREDUCE()
2071 case ISD::VECREDUCE_FMUL: CombineOpc = ISD::FMUL; break; in SplitVecOp_VECREDUCE()
2072 case ISD::VECREDUCE_ADD: CombineOpc = ISD::ADD; break; in SplitVecOp_VECREDUCE()
2073 case ISD::VECREDUCE_MUL: CombineOpc = ISD::MUL; break; in SplitVecOp_VECREDUCE()
2074 case ISD::VECREDUCE_AND: CombineOpc = ISD::AND; break; in SplitVecOp_VECREDUCE()
2075 case ISD::VECREDUCE_OR: CombineOpc = ISD::OR; break; in SplitVecOp_VECREDUCE()
2076 case ISD::VECREDUCE_XOR: CombineOpc = ISD::XOR; break; in SplitVecOp_VECREDUCE()
2077 case ISD::VECREDUCE_SMAX: CombineOpc = ISD::SMAX; break; in SplitVecOp_VECREDUCE()
2082 CombineOpc = NoNaN ? ISD::FMAXNUM : ISD::FMAXIMUM; in SplitVecOp_VECREDUCE()
[all …]
|
| /dports/devel/llvm90/llvm-9.0.1.src/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 2085 unsigned CombineOpc = 0; in SplitVecOp_VECREDUCE() local
2087 case ISD::VECREDUCE_FADD: CombineOpc = ISD::FADD; break; in SplitVecOp_VECREDUCE()
2088 case ISD::VECREDUCE_FMUL: CombineOpc = ISD::FMUL; break; in SplitVecOp_VECREDUCE()
2089 case ISD::VECREDUCE_ADD: CombineOpc = ISD::ADD; break; in SplitVecOp_VECREDUCE()
2090 case ISD::VECREDUCE_MUL: CombineOpc = ISD::MUL; break; in SplitVecOp_VECREDUCE()
2091 case ISD::VECREDUCE_AND: CombineOpc = ISD::AND; break; in SplitVecOp_VECREDUCE()
2092 case ISD::VECREDUCE_OR: CombineOpc = ISD::OR; break; in SplitVecOp_VECREDUCE()
2093 case ISD::VECREDUCE_XOR: CombineOpc = ISD::XOR; break; in SplitVecOp_VECREDUCE()
2094 case ISD::VECREDUCE_SMAX: CombineOpc = ISD::SMAX; break; in SplitVecOp_VECREDUCE()
2099 CombineOpc = NoNaN ? ISD::FMAXNUM : ISD::FMAXIMUM; in SplitVecOp_VECREDUCE()
[all …]
|
| /dports/devel/llvm80/llvm-8.0.1.src/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 3511 unsigned CombineOpc, unsigned ZeroReg = 0, in canCombine() argument
3519 if (!MI || MI->getParent() != &MBB || (unsigned)MI->getOpcode() != CombineOpc) in canCombine()
|
| /dports/devel/llvm70/llvm-7.0.1.src/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 3560 unsigned CombineOpc, unsigned ZeroReg = 0, in canCombine() argument
3568 if (!MI || MI->getParent() != &MBB || (unsigned)MI->getOpcode() != CombineOpc) in canCombine()
|
| /dports/devel/llvm90/llvm-9.0.1.src/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 3469 unsigned CombineOpc, unsigned ZeroReg = 0, in canCombine() argument
3477 if (!MI || MI->getParent() != &MBB || (unsigned)MI->getOpcode() != CombineOpc) in canCombine()
|
| /dports/devel/llvm10/llvm-10.0.1.src/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 3669 unsigned CombineOpc, unsigned ZeroReg = 0, in canCombine() argument
3677 if (!MI || MI->getParent() != &MBB || (unsigned)MI->getOpcode() != CombineOpc) in canCombine()
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 3669 unsigned CombineOpc, unsigned ZeroReg = 0, in canCombine() argument
3677 if (!MI || MI->getParent() != &MBB || (unsigned)MI->getOpcode() != CombineOpc) in canCombine()
|
| /dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 3669 unsigned CombineOpc, unsigned ZeroReg = 0, in canCombine() argument
3677 if (!MI || MI->getParent() != &MBB || (unsigned)MI->getOpcode() != CombineOpc) in canCombine()
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 2163 unsigned CombineOpc = ISD::getVecReduceBaseOpcode(N->getOpcode()); in SplitVecOp_VECREDUCE() local
2164 SDValue Partial = DAG.getNode(CombineOpc, dl, LoOpVT, Lo, Hi, N->getFlags()); in SplitVecOp_VECREDUCE()
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 4045 unsigned CombineOpc, unsigned ZeroReg = 0, in canCombine() argument
4053 if (!MI || MI->getParent() != &MBB || (unsigned)MI->getOpcode() != CombineOpc) in canCombine()
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 3872 unsigned CombineOpc, unsigned ZeroReg = 0, in canCombine() argument
3880 if (!MI || MI->getParent() != &MBB || (unsigned)MI->getOpcode() != CombineOpc) in canCombine()
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 4175 unsigned CombineOpc, unsigned ZeroReg = 0, in canCombine() argument
4183 if (!MI || MI->getParent() != &MBB || (unsigned)MI->getOpcode() != CombineOpc) in canCombine()
|
| /dports/devel/llvm11/llvm-11.0.1.src/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 3901 unsigned CombineOpc, unsigned ZeroReg = 0, in canCombine() argument
3909 if (!MI || MI->getParent() != &MBB || (unsigned)MI->getOpcode() != CombineOpc) in canCombine()
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 4175 unsigned CombineOpc, unsigned ZeroReg = 0, in canCombine() argument
4183 if (!MI || MI->getParent() != &MBB || (unsigned)MI->getOpcode() != CombineOpc) in canCombine()
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 2305 unsigned CombineOpc = ISD::getVecReduceBaseOpcode(N->getOpcode()); in SplitVecOp_VECREDUCE() local
2306 SDValue Partial = DAG.getNode(CombineOpc, dl, LoOpVT, Lo, Hi, N->getFlags()); in SplitVecOp_VECREDUCE()
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 4565 unsigned CombineOpc, unsigned ZeroReg = 0, in canCombine() argument
4573 if (!MI || MI->getParent() != &MBB || (unsigned)MI->getOpcode() != CombineOpc) in canCombine()
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 4565 unsigned CombineOpc, unsigned ZeroReg = 0, in canCombine() argument
4573 if (!MI || MI->getParent() != &MBB || (unsigned)MI->getOpcode() != CombineOpc) in canCombine()
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 2305 unsigned CombineOpc = ISD::getVecReduceBaseOpcode(N->getOpcode()); in SplitVecOp_VECREDUCE() local
2306 SDValue Partial = DAG.getNode(CombineOpc, dl, LoOpVT, Lo, Hi, N->getFlags()); in SplitVecOp_VECREDUCE()
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 2253 unsigned CombineOpc = ISD::getVecReduceBaseOpcode(N->getOpcode()); in SplitVecOp_VECREDUCE() local
2254 SDValue Partial = DAG.getNode(CombineOpc, dl, LoOpVT, Lo, Hi, N->getFlags()); in SplitVecOp_VECREDUCE()
|