| /dports/games/tenebrae/tenebrae_0/ |
| H A D | snd_gus.c | 554 static WORD CountReg; variable
888 CountReg=CountRegs[DmaChannel]; in GUS_StartDMA()
911 dos_outportb(CountReg, (count-1) & 0xff); in GUS_StartDMA()
912 dos_outportb(CountReg, (count-1) >> 8); in GUS_StartDMA()
921 dos_outportb(CountReg, ((count>>1)-1) & 0xff); in GUS_StartDMA()
922 dos_outportb(CountReg, ((count>>1)-1) >> 8); in GUS_StartDMA()
1224 count = dos_inportb(CountReg); in GUS_GetDMAPos()
1225 count += dos_inportb(CountReg) << 8; in GUS_GetDMAPos()
1233 count = dos_inportb(CountReg); in GUS_GetDMAPos()
1234 count += dos_inportb(CountReg) << 8; in GUS_GetDMAPos()
|
| /dports/games/uhexen2/hexen2source-1.5.9/engine/h2shared/ |
| H A D | snd_gus.c | 569 static WORD CountReg; variable
906 CountReg = CountRegs[dmaChannel]; in GUS_StartDMA()
929 dos_outportb(CountReg, (count - 1) & 0xff); in GUS_StartDMA()
930 dos_outportb(CountReg, (count - 1) >> 8); in GUS_StartDMA()
939 dos_outportb(CountReg, ((count >> 1) - 1) & 0xff); in GUS_StartDMA()
940 dos_outportb(CountReg, ((count >> 1) - 1) >> 8); in GUS_StartDMA()
1249 count = dos_inportb(CountReg); in S_GUS_GetDMAPos()
1250 count += dos_inportb(CountReg) << 8; in S_GUS_GetDMAPos()
1258 count = dos_inportb(CountReg); in S_GUS_GetDMAPos()
1259 count += dos_inportb(CountReg) << 8; in S_GUS_GetDMAPos()
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/ARM/ |
| H A D | MVEVPTOptimisationsPass.cpp | 206 Register CountReg = FirstVCTP->getOperand(1).getReg(); in ConvertTailPredLoop() local
207 if (!CountReg.isVirtual()) { in ConvertTailPredLoop()
211 MachineInstr *Phi = LookThroughCOPY(MRI->getVRegDef(CountReg), MRI); in ConvertTailPredLoop()
219 CountReg = Phi->getOperand(2).getMBB() == ML->getLoopLatch() in ConvertTailPredLoop()
238 .addReg(CountReg); in ConvertTailPredLoop()
242 MRI->constrainRegClass(CountReg, &ARM::rGPRRegClass); in ConvertTailPredLoop()
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/ARM/ |
| H A D | MVEVPTOptimisationsPass.cpp | 319 Register CountReg = FirstVCTP->getOperand(1).getReg(); in ConvertTailPredLoop() local
320 if (!CountReg.isVirtual()) { in ConvertTailPredLoop()
324 MachineInstr *Phi = LookThroughCOPY(MRI->getVRegDef(CountReg), MRI); in ConvertTailPredLoop()
332 CountReg = Phi->getOperand(2).getMBB() == ML->getLoopLatch() in ConvertTailPredLoop()
353 .addReg(CountReg); in ConvertTailPredLoop()
357 MRI->constrainRegClass(CountReg, &ARM::rGPRRegClass); in ConvertTailPredLoop()
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/ARM/ |
| H A D | MVEVPTOptimisationsPass.cpp | 319 Register CountReg = FirstVCTP->getOperand(1).getReg(); in ConvertTailPredLoop() local
320 if (!CountReg.isVirtual()) { in ConvertTailPredLoop()
324 MachineInstr *Phi = LookThroughCOPY(MRI->getVRegDef(CountReg), MRI); in ConvertTailPredLoop()
332 CountReg = Phi->getOperand(2).getMBB() == ML->getLoopLatch() in ConvertTailPredLoop()
353 .addReg(CountReg); in ConvertTailPredLoop()
357 MRI->constrainRegClass(CountReg, &ARM::rGPRRegClass); in ConvertTailPredLoop()
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/ARM/ |
| H A D | MVETPAndVPTOptimisationsPass.cpp | 468 Register CountReg = FirstVCTP->getOperand(1).getReg(); in ConvertTailPredLoop() local
469 if (!CountReg.isVirtual()) { in ConvertTailPredLoop()
473 MachineInstr *Phi = LookThroughCOPY(MRI->getVRegDef(CountReg), MRI); in ConvertTailPredLoop()
481 CountReg = Phi->getOperand(2).getMBB() == ML->getLoopLatch() in ConvertTailPredLoop()
505 .addReg(CountReg); in ConvertTailPredLoop()
510 MRI->constrainRegClass(CountReg, &ARM::rGPRRegClass); in ConvertTailPredLoop()
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/ARM/ |
| H A D | MVETPAndVPTOptimisationsPass.cpp | 468 Register CountReg = FirstVCTP->getOperand(1).getReg(); in ConvertTailPredLoop() local
469 if (!CountReg.isVirtual()) { in ConvertTailPredLoop()
473 MachineInstr *Phi = LookThroughCOPY(MRI->getVRegDef(CountReg), MRI); in ConvertTailPredLoop()
481 CountReg = Phi->getOperand(2).getMBB() == ML->getLoopLatch() in ConvertTailPredLoop()
505 .addReg(CountReg); in ConvertTailPredLoop()
510 MRI->constrainRegClass(CountReg, &ARM::rGPRRegClass); in ConvertTailPredLoop()
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/ARM/ |
| H A D | MVETPAndVPTOptimisationsPass.cpp | 468 Register CountReg = FirstVCTP->getOperand(1).getReg(); in ConvertTailPredLoop() local
469 if (!CountReg.isVirtual()) { in ConvertTailPredLoop()
473 MachineInstr *Phi = LookThroughCOPY(MRI->getVRegDef(CountReg), MRI); in ConvertTailPredLoop()
481 CountReg = Phi->getOperand(2).getMBB() == ML->getLoopLatch() in ConvertTailPredLoop()
505 .addReg(CountReg); in ConvertTailPredLoop()
510 MRI->constrainRegClass(CountReg, &ARM::rGPRRegClass); in ConvertTailPredLoop()
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/ARM/ |
| H A D | MVETPAndVPTOptimisationsPass.cpp | 468 Register CountReg = FirstVCTP->getOperand(1).getReg(); in ConvertTailPredLoop() local
469 if (!CountReg.isVirtual()) { in ConvertTailPredLoop()
473 MachineInstr *Phi = LookThroughCOPY(MRI->getVRegDef(CountReg), MRI); in ConvertTailPredLoop()
481 CountReg = Phi->getOperand(2).getMBB() == ML->getLoopLatch() in ConvertTailPredLoop()
505 .addReg(CountReg); in ConvertTailPredLoop()
510 MRI->constrainRegClass(CountReg, &ARM::rGPRRegClass); in ConvertTailPredLoop()
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/ARM/ |
| H A D | MVETPAndVPTOptimisationsPass.cpp | 468 Register CountReg = FirstVCTP->getOperand(1).getReg(); in ConvertTailPredLoop() local
469 if (!CountReg.isVirtual()) { in ConvertTailPredLoop()
473 MachineInstr *Phi = LookThroughCOPY(MRI->getVRegDef(CountReg), MRI); in ConvertTailPredLoop()
481 CountReg = Phi->getOperand(2).getMBB() == ML->getLoopLatch() in ConvertTailPredLoop()
505 .addReg(CountReg); in ConvertTailPredLoop()
510 MRI->constrainRegClass(CountReg, &ARM::rGPRRegClass); in ConvertTailPredLoop()
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/ARM/ |
| H A D | MVETPAndVPTOptimisationsPass.cpp | 477 Register CountReg = FirstVCTP->getOperand(1).getReg(); in ConvertTailPredLoop() local
478 if (!CountReg.isVirtual()) { in ConvertTailPredLoop()
482 MachineInstr *Phi = LookThroughCOPY(MRI->getVRegDef(CountReg), MRI); in ConvertTailPredLoop()
490 CountReg = Phi->getOperand(2).getMBB() == ML->getLoopLatch() in ConvertTailPredLoop()
514 .addReg(CountReg); in ConvertTailPredLoop()
519 MRI->constrainRegClass(CountReg, &ARM::rGPRRegClass); in ConvertTailPredLoop()
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/ |
| H A D | SILowerControlFlow.cpp | 685 Register CountReg = MRI->createVirtualRegister(&AMDGPU::SGPR_32RegClass); in lowerInitExec() local
686 auto BfeMI = BuildMI(*MBB, FirstMI, DL, TII->get(AMDGPU::S_BFE_U32), CountReg) in lowerInitExec()
692 .addReg(CountReg) in lowerInitExec()
695 .addReg(CountReg, RegState::Kill) in lowerInitExec()
718 LIS->createAndComputeVirtRegInterval(CountReg); in lowerInitExec()
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AMDGPU/ |
| H A D | SILowerControlFlow.cpp | 685 Register CountReg = MRI->createVirtualRegister(&AMDGPU::SGPR_32RegClass); in lowerInitExec() local
686 auto BfeMI = BuildMI(*MBB, FirstMI, DL, TII->get(AMDGPU::S_BFE_U32), CountReg) in lowerInitExec()
692 .addReg(CountReg) in lowerInitExec()
695 .addReg(CountReg, RegState::Kill) in lowerInitExec()
718 LIS->createAndComputeVirtRegInterval(CountReg); in lowerInitExec()
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/AMDGPU/ |
| H A D | SILowerControlFlow.cpp | 714 Register CountReg = MRI->createVirtualRegister(&AMDGPU::SGPR_32RegClass); in lowerInitExec() local
715 auto BfeMI = BuildMI(*MBB, FirstMI, DL, TII->get(AMDGPU::S_BFE_U32), CountReg) in lowerInitExec()
721 .addReg(CountReg) in lowerInitExec()
724 .addReg(CountReg, RegState::Kill) in lowerInitExec()
747 LIS->createAndComputeVirtRegInterval(CountReg); in lowerInitExec()
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SILowerControlFlow.cpp | 685 Register CountReg = MRI->createVirtualRegister(&AMDGPU::SGPR_32RegClass); in lowerInitExec() local
686 auto BfeMI = BuildMI(*MBB, FirstMI, DL, TII->get(AMDGPU::S_BFE_U32), CountReg) in lowerInitExec()
692 .addReg(CountReg) in lowerInitExec()
695 .addReg(CountReg, RegState::Kill) in lowerInitExec()
718 LIS->createAndComputeVirtRegInterval(CountReg); in lowerInitExec()
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/AMDGPU/ |
| H A D | SILowerControlFlow.cpp | 696 Register CountReg = MRI->createVirtualRegister(&AMDGPU::SGPR_32RegClass); in lowerInitExec() local
697 auto BfeMI = BuildMI(*MBB, FirstMI, DL, TII->get(AMDGPU::S_BFE_U32), CountReg) in lowerInitExec()
703 .addReg(CountReg) in lowerInitExec()
706 .addReg(CountReg, RegState::Kill) in lowerInitExec()
729 LIS->createAndComputeVirtRegInterval(CountReg); in lowerInitExec()
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/ |
| H A D | SILowerControlFlow.cpp | 685 Register CountReg = MRI->createVirtualRegister(&AMDGPU::SGPR_32RegClass); in lowerInitExec() local
686 auto BfeMI = BuildMI(*MBB, FirstMI, DL, TII->get(AMDGPU::S_BFE_U32), CountReg) in lowerInitExec()
692 .addReg(CountReg) in lowerInitExec()
695 .addReg(CountReg, RegState::Kill) in lowerInitExec()
718 LIS->createAndComputeVirtRegInterval(CountReg); in lowerInitExec()
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/AMDGPU/ |
| H A D | SILowerControlFlow.cpp | 714 Register CountReg = MRI->createVirtualRegister(&AMDGPU::SGPR_32RegClass); in lowerInitExec() local
715 auto BfeMI = BuildMI(*MBB, FirstMI, DL, TII->get(AMDGPU::S_BFE_U32), CountReg) in lowerInitExec()
721 .addReg(CountReg) in lowerInitExec()
724 .addReg(CountReg, RegState::Kill) in lowerInitExec()
747 LIS->createAndComputeVirtRegInterval(CountReg); in lowerInitExec()
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/ |
| H A D | SILowerControlFlow.cpp | 685 Register CountReg = MRI->createVirtualRegister(&AMDGPU::SGPR_32RegClass); in lowerInitExec() local
686 auto BfeMI = BuildMI(*MBB, FirstMI, DL, TII->get(AMDGPU::S_BFE_U32), CountReg) in lowerInitExec()
692 .addReg(CountReg) in lowerInitExec()
695 .addReg(CountReg, RegState::Kill) in lowerInitExec()
718 LIS->createAndComputeVirtRegInterval(CountReg); in lowerInitExec()
|
| /dports/devel/llvm10/llvm-10.0.1.src/lib/Target/ARM/ |
| H A D | ARMLowOverheadLoops.cpp | 269 unsigned CountReg = Start->getOperand(0).getReg(); in INITIALIZE_PASS() local
270 auto IsMoveLR = [&CountReg](MachineInstr *MI) { in INITIALIZE_PASS()
273 MI->getOperand(1).getReg() == CountReg && in INITIALIZE_PASS()
283 if (IsMoveLR(LRDef) && RDA->hasSameReachingDef(Start, LRDef, CountReg)) in INITIALIZE_PASS()
289 if (IsMoveLR(LRDef) && RDA->hasSameReachingDef(Start, LRDef, CountReg)) in INITIALIZE_PASS()
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| H A D | ARMLowOverheadLoops.cpp | 269 unsigned CountReg = Start->getOperand(0).getReg(); in INITIALIZE_PASS() local
270 auto IsMoveLR = [&CountReg](MachineInstr *MI) { in INITIALIZE_PASS()
273 MI->getOperand(1).getReg() == CountReg && in INITIALIZE_PASS()
283 if (IsMoveLR(LRDef) && RDA->hasSameReachingDef(Start, LRDef, CountReg)) in INITIALIZE_PASS()
289 if (IsMoveLR(LRDef) && RDA->hasSameReachingDef(Start, LRDef, CountReg)) in INITIALIZE_PASS()
|
| /dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMLowOverheadLoops.cpp | 269 unsigned CountReg = Start->getOperand(0).getReg(); in INITIALIZE_PASS() local
270 auto IsMoveLR = [&CountReg](MachineInstr *MI) { in INITIALIZE_PASS()
273 MI->getOperand(1).getReg() == CountReg && in INITIALIZE_PASS()
283 if (IsMoveLR(LRDef) && RDA->hasSameReachingDef(Start, LRDef, CountReg)) in INITIALIZE_PASS()
289 if (IsMoveLR(LRDef) && RDA->hasSameReachingDef(Start, LRDef, CountReg)) in INITIALIZE_PASS()
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/ARM/ |
| H A D | ARMLowOverheadLoops.cpp | 387 unsigned CountReg = Start->getOperand(0).getReg(); in INITIALIZE_PASS() local
388 auto IsMoveLR = [&CountReg](MachineInstr *MI) { in INITIALIZE_PASS()
391 MI->getOperand(1).getReg() == CountReg && in INITIALIZE_PASS()
401 if (IsMoveLR(LRDef) && RDA.hasSameReachingDef(Start, LRDef, CountReg)) in INITIALIZE_PASS()
407 if (IsMoveLR(LRDef) && RDA.hasSameReachingDef(Start, LRDef, CountReg)) in INITIALIZE_PASS()
|
| /dports/devel/llvm11/llvm-11.0.1.src/lib/Target/ARM/ |
| H A D | ARMLowOverheadLoops.cpp | 387 unsigned CountReg = Start->getOperand(0).getReg(); in INITIALIZE_PASS() local
388 auto IsMoveLR = [&CountReg](MachineInstr *MI) { in INITIALIZE_PASS()
391 MI->getOperand(1).getReg() == CountReg && in INITIALIZE_PASS()
401 if (IsMoveLR(LRDef) && RDA.hasSameReachingDef(Start, LRDef, CountReg)) in INITIALIZE_PASS()
407 if (IsMoveLR(LRDef) && RDA.hasSameReachingDef(Start, LRDef, CountReg)) in INITIALIZE_PASS()
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/Hexagon/ |
| H A D | HexagonHardwareLoops.cpp | 1248 Register CountReg = MRI->createVirtualRegister(&Hexagon::IntRegsRegClass); in convertToHardwareLoop() local
1249 BuildMI(*Preheader, InsertPos, DL, TII->get(TargetOpcode::COPY), CountReg) in convertToHardwareLoop()
1253 .addReg(CountReg); in convertToHardwareLoop()
1261 Register CountReg = MRI->createVirtualRegister(&Hexagon::IntRegsRegClass); in convertToHardwareLoop() local
1262 BuildMI(*Preheader, InsertPos, DL, TII->get(Hexagon::A2_tfrsi), CountReg) in convertToHardwareLoop()
1265 .addMBB(LoopStart).addReg(CountReg); in convertToHardwareLoop()
|