/dports/emulators/citra/citra-ac98458e0/externals/dynarmic/tests/A32/ |
H A D | test_arm_instructions.cpp | 105 REQUIRE(jit.Cpsr() == 0x200001d0); 146 REQUIRE(jit.Cpsr() == 0x000001d0); 173 REQUIRE(jit.Cpsr() == 0x000301d0); 201 REQUIRE(jit.Cpsr() == 0x080001d0); 224 REQUIRE(jit.Cpsr() == 0x000001d0); 240 REQUIRE(jit.Cpsr() == 0x000001d0); 268 REQUIRE(jit.Cpsr() == 0x000001d0); 295 REQUIRE(jit.Cpsr() == 0x000001d0); 346 REQUIRE(jit.Cpsr() == 0x000001d0); 396 REQUIRE(jit.Cpsr() == 0x000001d0); [all …]
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H A D | test_thumb_instructions.cpp | 38 REQUIRE(jit.Cpsr() == 0x00000030); 60 REQUIRE(jit.Cpsr() == 0xA0000030); // N, C flags, Thumb, User-mode 81 REQUIRE(jit.Cpsr() == 0x00000030); // Thumb, User-mode 101 REQUIRE(jit.Cpsr() == 0x00000030); // Thumb, User-mode 120 REQUIRE(jit.Cpsr() == 0x00000010); // User-mode 139 REQUIRE(jit.Cpsr() == 0x00000030); // Thumb, User-mode 158 REQUIRE(jit.Cpsr() == 0x00000030); // Thumb, User-mode
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/dports/emulators/citra-qt5/citra-ac98458e0/externals/dynarmic/tests/A32/ |
H A D | test_arm_instructions.cpp | 105 REQUIRE(jit.Cpsr() == 0x200001d0); 146 REQUIRE(jit.Cpsr() == 0x000001d0); 173 REQUIRE(jit.Cpsr() == 0x000301d0); 201 REQUIRE(jit.Cpsr() == 0x080001d0); 224 REQUIRE(jit.Cpsr() == 0x000001d0); 240 REQUIRE(jit.Cpsr() == 0x000001d0); 268 REQUIRE(jit.Cpsr() == 0x000001d0); 295 REQUIRE(jit.Cpsr() == 0x000001d0); 346 REQUIRE(jit.Cpsr() == 0x000001d0); 396 REQUIRE(jit.Cpsr() == 0x000001d0); [all …]
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H A D | test_thumb_instructions.cpp | 38 REQUIRE(jit.Cpsr() == 0x00000030); 60 REQUIRE(jit.Cpsr() == 0xA0000030); // N, C flags, Thumb, User-mode 81 REQUIRE(jit.Cpsr() == 0x00000030); // Thumb, User-mode 101 REQUIRE(jit.Cpsr() == 0x00000030); // Thumb, User-mode 120 REQUIRE(jit.Cpsr() == 0x00000010); // User-mode 139 REQUIRE(jit.Cpsr() == 0x00000030); // Thumb, User-mode 158 REQUIRE(jit.Cpsr() == 0x00000030); // Thumb, User-mode
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/dports/emulators/yuzu/yuzu-0b47f7a46/externals/dynarmic/tests/A32/ |
H A D | test_arm_instructions.cpp | 105 REQUIRE(jit.Cpsr() == 0x200001d0); 146 REQUIRE(jit.Cpsr() == 0x000001d0); 173 REQUIRE(jit.Cpsr() == 0x000301d0); 201 REQUIRE(jit.Cpsr() == 0x080001d0); 224 REQUIRE(jit.Cpsr() == 0x000001d0); 240 REQUIRE(jit.Cpsr() == 0x000001d0); 268 REQUIRE(jit.Cpsr() == 0x000001d0); 295 REQUIRE(jit.Cpsr() == 0x000001d0); 346 REQUIRE(jit.Cpsr() == 0x000001d0); 396 REQUIRE(jit.Cpsr() == 0x000001d0); [all …]
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H A D | test_thumb_instructions.cpp | 38 REQUIRE(jit.Cpsr() == 0x00000030); 60 REQUIRE(jit.Cpsr() == 0xA0000030); // N, C flags, Thumb, User-mode 81 REQUIRE(jit.Cpsr() == 0x00000030); // Thumb, User-mode 101 REQUIRE(jit.Cpsr() == 0x00000030); // Thumb, User-mode 120 REQUIRE(jit.Cpsr() == 0x00000010); // User-mode 139 REQUIRE(jit.Cpsr() == 0x00000030); // Thumb, User-mode 158 REQUIRE(jit.Cpsr() == 0x00000030); // Thumb, User-mode
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/dports/devel/avr-gdb/gdb-7.3.1/sim/arm/ |
H A D | armsupp.c | 130 state->Cpsr = value; in ARMul_SetCPSR() 147 SETPSR_C (state->Cpsr, rhs); in ARMul_FixCPSR() 149 SETPSR_X (state->Cpsr, rhs); in ARMul_FixCPSR() 220 state->Cpsr &= ~MODEBITS; in ARMul_CPSRAltered() 223 state->Cpsr &= ~INTBITS; in ARMul_CPSRAltered() 225 state->Cpsr &= ~NBIT; in ARMul_CPSRAltered() 227 state->Cpsr &= ~ZBIT; in ARMul_CPSRAltered() 229 state->Cpsr &= ~CBIT; in ARMul_CPSRAltered() 231 state->Cpsr &= ~VBIT; in ARMul_CPSRAltered() 233 state->Cpsr &= ~SBIT; in ARMul_CPSRAltered() [all …]
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/dports/devel/gdb761/gdb-7.6.1/sim/arm/ |
H A D | armsupp.c | 129 state->Cpsr = value; in ARMul_SetCPSR() 146 SETPSR_C (state->Cpsr, rhs); in ARMul_FixCPSR() 148 SETPSR_X (state->Cpsr, rhs); in ARMul_FixCPSR() 219 state->Cpsr &= ~MODEBITS; in ARMul_CPSRAltered() 222 state->Cpsr &= ~INTBITS; in ARMul_CPSRAltered() 224 state->Cpsr &= ~NBIT; in ARMul_CPSRAltered() 226 state->Cpsr &= ~ZBIT; in ARMul_CPSRAltered() 228 state->Cpsr &= ~CBIT; in ARMul_CPSRAltered() 230 state->Cpsr &= ~VBIT; in ARMul_CPSRAltered() 232 state->Cpsr &= ~SBIT; in ARMul_CPSRAltered() [all …]
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/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/gdb/sim/arm/ |
H A D | armsupp.c | 130 state->Cpsr = value; in ARMul_SetCPSR() 147 SETPSR_C (state->Cpsr, rhs); in ARMul_FixCPSR() 149 SETPSR_X (state->Cpsr, rhs); in ARMul_FixCPSR() 220 state->Cpsr &= ~MODEBITS; in ARMul_CPSRAltered() 223 state->Cpsr &= ~INTBITS; in ARMul_CPSRAltered() 225 state->Cpsr &= ~NBIT; in ARMul_CPSRAltered() 227 state->Cpsr &= ~ZBIT; in ARMul_CPSRAltered() 229 state->Cpsr &= ~CBIT; in ARMul_CPSRAltered() 231 state->Cpsr &= ~VBIT; in ARMul_CPSRAltered() 233 state->Cpsr &= ~SBIT; in ARMul_CPSRAltered() [all …]
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/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gdb/sim/arm/ |
H A D | armsupp.c | 130 state->Cpsr = value; in ARMul_SetCPSR() 147 SETPSR_C (state->Cpsr, rhs); in ARMul_FixCPSR() 149 SETPSR_X (state->Cpsr, rhs); in ARMul_FixCPSR() 220 state->Cpsr &= ~MODEBITS; in ARMul_CPSRAltered() 223 state->Cpsr &= ~INTBITS; in ARMul_CPSRAltered() 225 state->Cpsr &= ~NBIT; in ARMul_CPSRAltered() 227 state->Cpsr &= ~ZBIT; in ARMul_CPSRAltered() 229 state->Cpsr &= ~CBIT; in ARMul_CPSRAltered() 231 state->Cpsr &= ~VBIT; in ARMul_CPSRAltered() 233 state->Cpsr &= ~SBIT; in ARMul_CPSRAltered() [all …]
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/dports/emulators/citra/citra-ac98458e0/src/core/arm/dyncom/ |
H A D | arm_dyncom_interpreter.cpp | 1407 cpu->Cpsr = (cpu->Cpsr & 0x0fffffdf) | (cpu->NFlag << 31) | (cpu->ZFlag << 30) | \ in InterpreterMainLoop() 1637 if (!(cpu->Cpsr & 0x80)) { in InterpreterMainLoop() 1971 cpu->Cpsr = (cpu->Cpsr & aif_mask) | aif_val; in InterpreterMainLoop() 1974 cpu->Cpsr = (cpu->Cpsr & 0xffffffe0) | inst_cream->mode; in InterpreterMainLoop() 2446 cpu->Cpsr = (cpu->Cpsr & ~0xF0000000) | (value & 0xF0000000); in InterpreterMainLoop() 2484 RD = cpu->Cpsr; in InterpreterMainLoop() 2520 cpu->Cpsr = (cpu->Cpsr & ~mask) | (operand & mask); in InterpreterMainLoop() 3050 const u32 cpsr = cpu->Cpsr; in InterpreterMainLoop() 3088 cpu->Cpsr |= (1 << 9); in InterpreterMainLoop() 3090 cpu->Cpsr &= ~(1 << 9); in InterpreterMainLoop() [all …]
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H A D | arm_dyncom.cpp | 141 return state->Cpsr; in GetCPSR() 145 state->Cpsr = cpsr; in SetCPSR() 174 ctx->cpsr = state->Cpsr; in SaveContext() 185 state->Cpsr = ctx->cpsr; in LoadContext()
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/dports/emulators/citra-qt5/citra-ac98458e0/src/core/arm/dyncom/ |
H A D | arm_dyncom_interpreter.cpp | 1407 cpu->Cpsr = (cpu->Cpsr & 0x0fffffdf) | (cpu->NFlag << 31) | (cpu->ZFlag << 30) | \ in InterpreterMainLoop() 1637 if (!(cpu->Cpsr & 0x80)) { in InterpreterMainLoop() 1971 cpu->Cpsr = (cpu->Cpsr & aif_mask) | aif_val; in InterpreterMainLoop() 1974 cpu->Cpsr = (cpu->Cpsr & 0xffffffe0) | inst_cream->mode; in InterpreterMainLoop() 2446 cpu->Cpsr = (cpu->Cpsr & ~0xF0000000) | (value & 0xF0000000); in InterpreterMainLoop() 2484 RD = cpu->Cpsr; in InterpreterMainLoop() 2520 cpu->Cpsr = (cpu->Cpsr & ~mask) | (operand & mask); in InterpreterMainLoop() 3050 const u32 cpsr = cpu->Cpsr; in InterpreterMainLoop() 3088 cpu->Cpsr |= (1 << 9); in InterpreterMainLoop() 3090 cpu->Cpsr &= ~(1 << 9); in InterpreterMainLoop() [all …]
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H A D | arm_dyncom.cpp | 141 return state->Cpsr; in GetCPSR() 145 state->Cpsr = cpsr; in SetCPSR() 174 ctx->cpsr = state->Cpsr; in SaveContext() 185 state->Cpsr = ctx->cpsr; in LoadContext()
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/dports/emulators/qemu60/qemu-6.0.0/roms/edk2/ArmPkg/Library/DefaultExceptionHandlerLib/Arm/ |
H A D | DefaultExceptionHandler.c | 57 IN UINT32 Cpsr, in CpsrString() argument 82 if ((Cpsr & (1 << CpsrChar[Index].BIT)) != 0) { in CpsrString() 91 switch (Cpsr & 0x1f) { in CpsrString()
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/dports/emulators/qemu42/qemu-4.2.1/roms/edk2/ArmPkg/Library/DefaultExceptionHandlerLib/Arm/ |
H A D | DefaultExceptionHandler.c | 57 IN UINT32 Cpsr, in CpsrString() argument 82 if ((Cpsr & (1 << CpsrChar[Index].BIT)) != 0) { in CpsrString() 91 switch (Cpsr & 0x1f) { in CpsrString()
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/dports/emulators/qemu/qemu-6.2.0/roms/edk2/ArmPkg/Library/DefaultExceptionHandlerLib/Arm/ |
H A D | DefaultExceptionHandler.c | 57 IN UINT32 Cpsr, in CpsrString() argument 82 if ((Cpsr & (1 << CpsrChar[Index].BIT)) != 0) { in CpsrString() 91 switch (Cpsr & 0x1f) { in CpsrString()
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/dports/emulators/qemu-utils/qemu-4.2.1/roms/edk2/ArmPkg/Library/DefaultExceptionHandlerLib/Arm/ |
H A D | DefaultExceptionHandler.c | 57 IN UINT32 Cpsr, in CpsrString() argument 82 if ((Cpsr & (1 << CpsrChar[Index].BIT)) != 0) { in CpsrString() 91 switch (Cpsr & 0x1f) { in CpsrString()
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/dports/emulators/qemu5/qemu-5.2.0/roms/edk2/ArmPkg/Library/DefaultExceptionHandlerLib/Arm/ |
H A D | DefaultExceptionHandler.c | 57 IN UINT32 Cpsr, in CpsrString() argument 82 if ((Cpsr & (1 << CpsrChar[Index].BIT)) != 0) { in CpsrString() 91 switch (Cpsr & 0x1f) { in CpsrString()
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/dports/sysutils/uefi-edk2-qemu/edk2-edk2-stable201911/ArmPkg/Library/DefaultExceptionHandlerLib/Arm/ |
H A D | DefaultExceptionHandler.c | 57 IN UINT32 Cpsr, in CpsrString() argument 82 if ((Cpsr & (1 << CpsrChar[Index].BIT)) != 0) { in CpsrString() 91 switch (Cpsr & 0x1f) { in CpsrString()
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/dports/sysutils/uefi-edk2-bhyve-csm/uefi-edk2-aa8d718/ArmPkg/Library/DefaultExceptionHandlerLib/Arm/ |
H A D | DefaultExceptionHandler.c | 56 IN UINT32 Cpsr, in CpsrString() argument 81 if ((Cpsr & (1 << CpsrChar[Index].BIT)) != 0) { in CpsrString() 90 switch (Cpsr & 0x1f) { in CpsrString()
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/edk2/ArmPkg/Library/DefaultExceptionHandlerLib/Arm/ |
H A D | DefaultExceptionHandler.c | 57 IN UINT32 Cpsr, in CpsrString() argument 82 if ((Cpsr & (1 << CpsrChar[Index].BIT)) != 0) { in CpsrString() 91 switch (Cpsr & 0x1f) { in CpsrString()
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/dports/sysutils/uefi-edk2-bhyve/edk2-edk2-stable202102/ArmPkg/Library/DefaultExceptionHandlerLib/Arm/ |
H A D | DefaultExceptionHandler.c | 71 IN UINT32 Cpsr, in CpsrString() argument 83 if ((Cpsr & (1 << mCpsrChar[Index].BIT)) != 0) { in CpsrString() 92 switch (Cpsr & 0x1f) { in CpsrString()
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/dports/sysutils/edk2/edk2-edk2-stable202102/ArmPkg/Library/DefaultExceptionHandlerLib/Arm/ |
H A D | DefaultExceptionHandler.c | 71 IN UINT32 Cpsr, 83 if ((Cpsr & (1 << mCpsrChar[Index].BIT)) != 0) { 92 switch (Cpsr & 0x1f) {
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/dports/emulators/yuzu/yuzu-0b47f7a46/externals/dynarmic/src/backend/x64/ |
H A D | a32_interface.cpp | 268 u32 Jit::Cpsr() const { in Cpsr() function in Dynarmic::A32::Jit 269 return impl->jit_state.Cpsr(); in Cpsr() 321 std::uint32_t Context::Cpsr() const { in Cpsr() function in Dynarmic::A32::Context 322 return impl->jit_state.Cpsr(); in Cpsr()
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