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Searched refs:DAVINCI_PLL_CNTRL1_BASE (Results 1 – 25 of 146) sorted by relevance

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/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/arm/mach-davinci/
H A Dcpu.c188 pllbase = DAVINCI_PLL_CNTRL1_BASE; in set_cpu_clk_info()
199 pllbase = DAVINCI_PLL_CNTRL1_BASE; in set_cpu_clk_info()
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/arm/mach-davinci/
H A Dcpu.c188 pllbase = DAVINCI_PLL_CNTRL1_BASE; in set_cpu_clk_info()
199 pllbase = DAVINCI_PLL_CNTRL1_BASE; in set_cpu_clk_info()
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/arm/mach-davinci/
H A Dcpu.c188 pllbase = DAVINCI_PLL_CNTRL1_BASE; in set_cpu_clk_info()
199 pllbase = DAVINCI_PLL_CNTRL1_BASE; in set_cpu_clk_info()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/arm/mach-davinci/
H A Dcpu.c188 pllbase = DAVINCI_PLL_CNTRL1_BASE; in set_cpu_clk_info()
199 pllbase = DAVINCI_PLL_CNTRL1_BASE; in set_cpu_clk_info()
/dports/sysutils/u-boot-utilite/u-boot-2015.07/arch/arm/mach-davinci/
H A Dcpu.c191 pllbase = DAVINCI_PLL_CNTRL1_BASE; in set_cpu_clk_info()
202 pllbase = DAVINCI_PLL_CNTRL1_BASE; in set_cpu_clk_info()
/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot/arch/arm/mach-davinci/
H A Dcpu.c188 pllbase = DAVINCI_PLL_CNTRL1_BASE; in set_cpu_clk_info()
199 pllbase = DAVINCI_PLL_CNTRL1_BASE; in set_cpu_clk_info()
/dports/sysutils/u-boot-utilite/u-boot-2015.07/arch/arm/mach-davinci/include/mach/
H A Dhardware.h51 #define DAVINCI_PLL_CNTRL1_BASE (0x01c40c00) macro
119 #define DAVINCI_PLL_CNTRL1_BASE 0x01e1a000 macro
425 #define davinci_pllc1_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL1_BASE)
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/arm/mach-davinci/include/mach/
H A Dhardware.h51 #define DAVINCI_PLL_CNTRL1_BASE (0x01c40c00) macro
119 #define DAVINCI_PLL_CNTRL1_BASE 0x01e1a000 macro
426 #define davinci_pllc1_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL1_BASE)
H A Dpll_defs.h75 #define dv_pll1_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL1_BASE)
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/arm/mach-davinci/include/mach/
H A Dhardware.h51 #define DAVINCI_PLL_CNTRL1_BASE (0x01c40c00) macro
119 #define DAVINCI_PLL_CNTRL1_BASE 0x01e1a000 macro
426 #define davinci_pllc1_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL1_BASE)
H A Dpll_defs.h75 #define dv_pll1_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL1_BASE)
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/arm/mach-davinci/include/mach/
H A Dhardware.h51 #define DAVINCI_PLL_CNTRL1_BASE (0x01c40c00) macro
119 #define DAVINCI_PLL_CNTRL1_BASE 0x01e1a000 macro
426 #define davinci_pllc1_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL1_BASE)
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/arm/mach-davinci/include/mach/
H A Dhardware.h51 #define DAVINCI_PLL_CNTRL1_BASE (0x01c40c00) macro
119 #define DAVINCI_PLL_CNTRL1_BASE 0x01e1a000 macro
426 #define davinci_pllc1_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL1_BASE)
/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot/arch/arm/mach-davinci/include/mach/
H A Dhardware.h51 #define DAVINCI_PLL_CNTRL1_BASE (0x01c40c00) macro
119 #define DAVINCI_PLL_CNTRL1_BASE 0x01e1a000 macro
426 #define davinci_pllc1_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL1_BASE)
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/mach-davinci/include/mach/
H A Dpll_defs.h75 #define dv_pll1_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL1_BASE)
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/mach-davinci/include/mach/
H A Dpll_defs.h75 #define dv_pll1_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL1_BASE)
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/arm/mach-davinci/include/mach/
H A Dpll_defs.h75 #define dv_pll1_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL1_BASE)
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/mach-davinci/include/mach/
H A Dpll_defs.h75 #define dv_pll1_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL1_BASE)
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/arm/mach-davinci/include/mach/
H A Dpll_defs.h75 #define dv_pll1_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL1_BASE)
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/mach-davinci/include/mach/
H A Dpll_defs.h75 #define dv_pll1_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL1_BASE)
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/mach-davinci/include/mach/
H A Dpll_defs.h75 #define dv_pll1_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL1_BASE)
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/arm/mach-davinci/include/mach/
H A Dpll_defs.h75 #define dv_pll1_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL1_BASE)
/dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/arm/mach-davinci/include/mach/
H A Dpll_defs.h75 #define dv_pll1_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL1_BASE)
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/arm/mach-davinci/include/mach/
H A Dpll_defs.h75 #define dv_pll1_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL1_BASE)
/dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/arm/mach-davinci/include/mach/
H A Dpll_defs.h75 #define dv_pll1_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL1_BASE)

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