| /dports/sysutils/atf-sun50i_h6/arm-trusted-firmware-2.5/plat/st/stm32mp1/ |
| H A D | stm32mp1_dbgmcu.c | 26 #define DBGMCU_APB4FZ1_IWDG2 BIT(2) macro
92 DBGMCU_APB4FZ1_IWDG2); in stm32mp1_dbgmcu_freeze_iwdg2()
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| /dports/sysutils/atf-sun50i_a64/arm-trusted-firmware-2.5/plat/st/stm32mp1/ |
| H A D | stm32mp1_dbgmcu.c | 26 #define DBGMCU_APB4FZ1_IWDG2 BIT(2) macro
92 DBGMCU_APB4FZ1_IWDG2); in stm32mp1_dbgmcu_freeze_iwdg2()
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| /dports/sysutils/atf-rk3399/arm-trusted-firmware-2.5/plat/st/stm32mp1/ |
| H A D | stm32mp1_dbgmcu.c | 26 #define DBGMCU_APB4FZ1_IWDG2 BIT(2) macro
92 DBGMCU_APB4FZ1_IWDG2); in stm32mp1_dbgmcu_freeze_iwdg2()
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| /dports/sysutils/atf-fvp/arm-trusted-firmware-2.5/plat/st/stm32mp1/ |
| H A D | stm32mp1_dbgmcu.c | 26 #define DBGMCU_APB4FZ1_IWDG2 BIT(2) macro
92 DBGMCU_APB4FZ1_IWDG2); in stm32mp1_dbgmcu_freeze_iwdg2()
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| /dports/sysutils/atf-rk3328/arm-trusted-firmware-2.5/plat/st/stm32mp1/ |
| H A D | stm32mp1_dbgmcu.c | 26 #define DBGMCU_APB4FZ1_IWDG2 BIT(2) macro
92 DBGMCU_APB4FZ1_IWDG2); in stm32mp1_dbgmcu_freeze_iwdg2()
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| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/arm/mach-stm32mp/ |
| H A D | cpu.c | 41 #define DBGMCU_APB4FZ1_IWDG2 BIT(2) macro
126 setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2); in dbgmcu_init()
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| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/arm/mach-stm32mp/ |
| H A D | cpu.c | 41 #define DBGMCU_APB4FZ1_IWDG2 BIT(2) macro
126 setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2); in dbgmcu_init()
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| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/arm/mach-stm32mp/ |
| H A D | cpu.c | 41 #define DBGMCU_APB4FZ1_IWDG2 BIT(2) macro
126 setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2); in dbgmcu_init()
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| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/arm/mach-stm32mp/ |
| H A D | cpu.c | 41 #define DBGMCU_APB4FZ1_IWDG2 BIT(2) macro
126 setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2); in dbgmcu_init()
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| /dports/emulators/qemu60/qemu-6.0.0/roms/u-boot/arch/arm/mach-stm32mp/ |
| H A D | cpu.c | 41 #define DBGMCU_APB4FZ1_IWDG2 BIT(2) macro
126 setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2); in dbgmcu_init()
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| /dports/sysutils/u-boot-tools/u-boot-2020.07/arch/arm/mach-stm32mp/ |
| H A D | cpu.c | 49 #define DBGMCU_APB4FZ1_IWDG2 BIT(2) macro
159 setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2); in dbgmcu_init()
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| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/mach-stm32mp/ |
| H A D | cpu.c | 54 #define DBGMCU_APB4FZ1_IWDG2 BIT(2) macro
168 setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2); in dbgmcu_init()
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| /dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/arm/mach-stm32mp/ |
| H A D | cpu.c | 54 #define DBGMCU_APB4FZ1_IWDG2 BIT(2) macro
168 setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2); in dbgmcu_init()
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| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/mach-stm32mp/ |
| H A D | cpu.c | 54 #define DBGMCU_APB4FZ1_IWDG2 BIT(2) macro
168 setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2); in dbgmcu_init()
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| /dports/sysutils/u-boot-chip/u-boot-2021.07/arch/arm/mach-stm32mp/ |
| H A D | cpu.c | 54 #define DBGMCU_APB4FZ1_IWDG2 BIT(2) macro
168 setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2); in dbgmcu_init()
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| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/mach-stm32mp/ |
| H A D | cpu.c | 54 #define DBGMCU_APB4FZ1_IWDG2 BIT(2) macro
168 setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2); in dbgmcu_init()
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| /dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/arm/mach-stm32mp/ |
| H A D | cpu.c | 54 #define DBGMCU_APB4FZ1_IWDG2 BIT(2) macro
168 setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2); in dbgmcu_init()
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| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/arm/mach-stm32mp/ |
| H A D | cpu.c | 54 #define DBGMCU_APB4FZ1_IWDG2 BIT(2) macro
168 setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2); in dbgmcu_init()
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| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/mach-stm32mp/ |
| H A D | cpu.c | 54 #define DBGMCU_APB4FZ1_IWDG2 BIT(2) macro
168 setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2); in dbgmcu_init()
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| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/arm/mach-stm32mp/ |
| H A D | cpu.c | 54 #define DBGMCU_APB4FZ1_IWDG2 BIT(2) macro
168 setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2); in dbgmcu_init()
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| /dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/arm/mach-stm32mp/ |
| H A D | cpu.c | 54 #define DBGMCU_APB4FZ1_IWDG2 BIT(2) macro
168 setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2); in dbgmcu_init()
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/arm/mach-stm32mp/ |
| H A D | cpu.c | 54 #define DBGMCU_APB4FZ1_IWDG2 BIT(2) macro
168 setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2); in dbgmcu_init()
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/mach-stm32mp/ |
| H A D | cpu.c | 54 #define DBGMCU_APB4FZ1_IWDG2 BIT(2) macro
168 setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2); in dbgmcu_init()
|
| /dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/arm/mach-stm32mp/ |
| H A D | cpu.c | 54 #define DBGMCU_APB4FZ1_IWDG2 BIT(2) macro
168 setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2); in dbgmcu_init()
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| /dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/arch/arm/mach-stm32mp/ |
| H A D | cpu.c | 54 #define DBGMCU_APB4FZ1_IWDG2 BIT(2) macro
168 setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2); in dbgmcu_init()
|