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Searched refs:DBGMCU_CR_DBG_STANDBY (Results 1 – 25 of 29) sorted by relevance

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/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32G4xx_HAL_Driver/src/
H A Dstm32g4xx_hal.c537 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); in HAL_DBGMCU_EnableDBGStandbyMode()
546 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); in HAL_DBGMCU_DisableDBGStandbyMode()
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32F0xx_StdPeriph_Driver/inc/
H A Dstm32f0xx_dbgmcu.h56 #define DBGMCU_STANDBY DBGMCU_CR_DBG_STANDBY
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32F37x_StdPeriph_Driver/inc/
H A Dstm32f37x_dbgmcu.h55 #define DBGMCU_STANDBY DBGMCU_CR_DBG_STANDBY
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/STM32F37x_StdPeriph_Driver/inc/
H A Dstm32f37x_dbgmcu.h55 #define DBGMCU_STANDBY DBGMCU_CR_DBG_STANDBY
/dports/security/py-ailment/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/
H A Dstm32l1xx_ll_system.h832 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); in LL_DBGMCU_EnableDBGStandbyMode()
842 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); in LL_DBGMCU_DisableDBGStandbyMode()
/dports/security/py-pyvex/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/
H A Dstm32l1xx_ll_system.h832 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); in LL_DBGMCU_EnableDBGStandbyMode()
842 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); in LL_DBGMCU_DisableDBGStandbyMode()
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32G4xx_HAL_Driver/inc/
H A Dstm32g4xx_ll_system.h983 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); in LL_DBGMCU_EnableDBGStandbyMode()
993 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); in LL_DBGMCU_DisableDBGStandbyMode()
/dports/devel/py-cle/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/
H A Dstm32l1xx_ll_system.h832 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); in LL_DBGMCU_EnableDBGStandbyMode()
842 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); in LL_DBGMCU_DisableDBGStandbyMode()
/dports/security/py-angr/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/
H A Dstm32l1xx_ll_system.h832 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); in LL_DBGMCU_EnableDBGStandbyMode()
842 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); in LL_DBGMCU_DisableDBGStandbyMode()
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/CMSIS/CM3_f37x/
H A Dstm32f37x.h2735 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) macro
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/CMSIS/CM3_f0xx/
H A Dstm32f0xx.h2818 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode … macro
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/CMSIS/CM3_f37x/
H A Dstm32f37x.h2735 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) macro
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/CMSIS/CM3_f10x/
H A Dstm32f10x.h7281 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!<Debug Standby mode */ macro
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/CMSIS/CM3_f10x/
H A Dstm32f10x.h7281 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!<Debug Standby mode */ macro
/dports/security/py-pyvex/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/
H A Dstm32l152xe.h2055 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby m… macro
/dports/devel/py-cle/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/
H A Dstm32l152xe.h2055 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby m… macro
/dports/security/py-angr/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/
H A Dstm32l152xe.h2055 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby m… macro
/dports/security/py-ailment/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/
H A Dstm32l152xe.h2055 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby m… macro
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/CMSIS/CM3_f30x/
H A Dstm32f30x.h5251 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) macro
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/CMSIS/CM3_f4xx/
H A Dstm32f4xx.h10935 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) macro
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/CMSIS/CM3_f4xx/
H A Dstm32f4xx.h10935 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) macro
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/CMSIS/CM3_g4xx/
H A Dstm32g431xx.h2828 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk macro
H A Dstm32gbk1cb.h2814 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk macro
H A Dstm32g441xx.h3050 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk macro
H A Dstm32g471xx.h2892 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk macro

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