| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/ |
| H A D | bedbug_405.c | 160 if (dbsr_val & DBSR_IA1) { in bedbug405_break_isr()
163 SET_DBSR (DBSR_IA1); /* Write a 1 to clear */ in bedbug405_break_isr()
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| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/ |
| H A D | bedbug_405.c | 160 if (dbsr_val & DBSR_IA1) { in bedbug405_break_isr()
163 SET_DBSR (DBSR_IA1); /* Write a 1 to clear */ in bedbug405_break_isr()
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| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/ |
| H A D | bedbug_405.c | 160 if (dbsr_val & DBSR_IA1) { in bedbug405_break_isr()
163 SET_DBSR (DBSR_IA1); /* Write a 1 to clear */ in bedbug405_break_isr()
|
| /dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/ |
| H A D | bedbug_405.c | 160 if (dbsr_val & DBSR_IA1) { in bedbug405_break_isr()
163 SET_DBSR (DBSR_IA1); /* Write a 1 to clear */ in bedbug405_break_isr()
|
| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/ |
| H A D | bedbug_405.c | 160 if (dbsr_val & DBSR_IA1) { in bedbug405_break_isr()
163 SET_DBSR (DBSR_IA1); /* Write a 1 to clear */ in bedbug405_break_isr()
|
| /dports/emulators/qemu/qemu-6.2.0/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/ |
| H A D | bedbug_405.c | 160 if (dbsr_val & DBSR_IA1) { in bedbug405_break_isr()
163 SET_DBSR (DBSR_IA1); /* Write a 1 to clear */ in bedbug405_break_isr()
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| /dports/sysutils/u-boot-utilite/u-boot-2015.07/arch/powerpc/cpu/ppc4xx/ |
| H A D | bedbug_405.c | 160 if (dbsr_val & DBSR_IA1) { in bedbug405_break_isr()
163 SET_DBSR (DBSR_IA1); /* Write a 1 to clear */ in bedbug405_break_isr()
|
| /dports/emulators/qemu60/qemu-6.0.0/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/ |
| H A D | bedbug_405.c | 160 if (dbsr_val & DBSR_IA1) { in bedbug405_break_isr()
163 SET_DBSR (DBSR_IA1); /* Write a 1 to clear */ in bedbug405_break_isr()
|
| /dports/misc/rump/buildrump.sh-b914579/src/sys/arch/powerpc/include/ibm4xx/ |
| H A D | spr.h | 137 #define DBSR_IA1 0x04000000 /* IAC1 debug event */ macro
|
| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/include/bedbug/ |
| H A D | regs.h | 150 #define DBSR_IA1 0x00800000 /* Instr Address Compare 1 Event */ macro
155 #define DBSR_IA1 0x04000000 /* Instr Address Compare 1 Event */ macro
|
| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/include/bedbug/ |
| H A D | regs.h | 150 #define DBSR_IA1 0x00800000 /* Instr Address Compare 1 Event */ macro
155 #define DBSR_IA1 0x04000000 /* Instr Address Compare 1 Event */ macro
|
| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/include/bedbug/ |
| H A D | regs.h | 150 #define DBSR_IA1 0x00800000 /* Instr Address Compare 1 Event */ macro
155 #define DBSR_IA1 0x04000000 /* Instr Address Compare 1 Event */ macro
|
| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/include/bedbug/ |
| H A D | regs.h | 150 #define DBSR_IA1 0x00800000 /* Instr Address Compare 1 Event */ macro
155 #define DBSR_IA1 0x04000000 /* Instr Address Compare 1 Event */ macro
|
| /dports/sysutils/u-boot-wandboard/u-boot-2021.07/include/bedbug/ |
| H A D | regs.h | 150 #define DBSR_IA1 0x00800000 /* Instr Address Compare 1 Event */ macro
155 #define DBSR_IA1 0x04000000 /* Instr Address Compare 1 Event */ macro
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/include/bedbug/ |
| H A D | regs.h | 150 #define DBSR_IA1 0x00800000 /* Instr Address Compare 1 Event */ macro
155 #define DBSR_IA1 0x04000000 /* Instr Address Compare 1 Event */ macro
|
| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/include/bedbug/ |
| H A D | regs.h | 150 #define DBSR_IA1 0x00800000 /* Instr Address Compare 1 Event */ macro
155 #define DBSR_IA1 0x04000000 /* Instr Address Compare 1 Event */ macro
|
| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/include/bedbug/ |
| H A D | regs.h | 150 #define DBSR_IA1 0x00800000 /* Instr Address Compare 1 Event */ macro
155 #define DBSR_IA1 0x04000000 /* Instr Address Compare 1 Event */ macro
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/include/bedbug/ |
| H A D | regs.h | 150 #define DBSR_IA1 0x00800000 /* Instr Address Compare 1 Event */ macro
155 #define DBSR_IA1 0x04000000 /* Instr Address Compare 1 Event */ macro
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/include/bedbug/ |
| H A D | regs.h | 150 #define DBSR_IA1 0x00800000 /* Instr Address Compare 1 Event */ macro
155 #define DBSR_IA1 0x04000000 /* Instr Address Compare 1 Event */ macro
|
| /dports/sysutils/u-boot-rpi/u-boot-2021.07/include/bedbug/ |
| H A D | regs.h | 150 #define DBSR_IA1 0x00800000 /* Instr Address Compare 1 Event */ macro
155 #define DBSR_IA1 0x04000000 /* Instr Address Compare 1 Event */ macro
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/include/bedbug/ |
| H A D | regs.h | 150 #define DBSR_IA1 0x00800000 /* Instr Address Compare 1 Event */ macro
155 #define DBSR_IA1 0x04000000 /* Instr Address Compare 1 Event */ macro
|
| /dports/sysutils/u-boot-nanopi-neo2/u-boot-2021.07/include/bedbug/ |
| H A D | regs.h | 150 #define DBSR_IA1 0x00800000 /* Instr Address Compare 1 Event */ macro
155 #define DBSR_IA1 0x04000000 /* Instr Address Compare 1 Event */ macro
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/include/bedbug/ |
| H A D | regs.h | 150 #define DBSR_IA1 0x00800000 /* Instr Address Compare 1 Event */ macro
155 #define DBSR_IA1 0x04000000 /* Instr Address Compare 1 Event */ macro
|
| /dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/include/bedbug/ |
| H A D | regs.h | 150 #define DBSR_IA1 0x00800000 /* Instr Address Compare 1 Event */ macro
155 #define DBSR_IA1 0x04000000 /* Instr Address Compare 1 Event */ macro
|
| /dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/include/bedbug/ |
| H A D | regs.h | 150 #define DBSR_IA1 0x00800000 /* Instr Address Compare 1 Event */ macro
155 #define DBSR_IA1 0x04000000 /* Instr Address Compare 1 Event */ macro
|