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Searched refs:DBTRAIN_TEST (Results 1 – 25 of 56) sorted by relevance

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/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/ram/octeon/
H A Docteon3_lmc.c72 #define DBTRAIN_TEST 0 macro
5364 DBTRAIN_TEST, bad_bits); in lmc_sw_write_leveling_loop()
5604 DBTRAIN_TEST, in parallel_wl_block_delay()
6027 DBTRAIN_TEST, in lmc_sw_write_leveling()
10215 case DBTRAIN_TEST: // always choose LFSR if chip supports it in choose_best_hw_patterns()
10236 new_mode = DBTRAIN_TEST; in choose_best_hw_patterns()
10305 int mode = choose_best_hw_patterns(lmc, DBTRAIN_TEST); in hw_assist_test_dll_offset()
10334 if (mode == DBTRAIN_TEST) { in hw_assist_test_dll_offset()
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/ram/octeon/
H A Docteon3_lmc.c72 #define DBTRAIN_TEST 0 macro
5364 DBTRAIN_TEST, bad_bits); in lmc_sw_write_leveling_loop()
5604 DBTRAIN_TEST, in parallel_wl_block_delay()
6027 DBTRAIN_TEST, in lmc_sw_write_leveling()
10215 case DBTRAIN_TEST: // always choose LFSR if chip supports it in choose_best_hw_patterns()
10236 new_mode = DBTRAIN_TEST; in choose_best_hw_patterns()
10305 int mode = choose_best_hw_patterns(lmc, DBTRAIN_TEST); in hw_assist_test_dll_offset()
10334 if (mode == DBTRAIN_TEST) { in hw_assist_test_dll_offset()
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/ram/octeon/
H A Docteon3_lmc.c72 #define DBTRAIN_TEST 0 macro
5364 DBTRAIN_TEST, bad_bits); in lmc_sw_write_leveling_loop()
5604 DBTRAIN_TEST, in parallel_wl_block_delay()
6027 DBTRAIN_TEST, in lmc_sw_write_leveling()
10215 case DBTRAIN_TEST: // always choose LFSR if chip supports it in choose_best_hw_patterns()
10236 new_mode = DBTRAIN_TEST; in choose_best_hw_patterns()
10305 int mode = choose_best_hw_patterns(lmc, DBTRAIN_TEST); in hw_assist_test_dll_offset()
10334 if (mode == DBTRAIN_TEST) { in hw_assist_test_dll_offset()
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/ram/octeon/
H A Docteon3_lmc.c72 #define DBTRAIN_TEST 0 macro
5364 DBTRAIN_TEST, bad_bits); in lmc_sw_write_leveling_loop()
5604 DBTRAIN_TEST, in parallel_wl_block_delay()
6027 DBTRAIN_TEST, in lmc_sw_write_leveling()
10215 case DBTRAIN_TEST: // always choose LFSR if chip supports it in choose_best_hw_patterns()
10236 new_mode = DBTRAIN_TEST; in choose_best_hw_patterns()
10305 int mode = choose_best_hw_patterns(lmc, DBTRAIN_TEST); in hw_assist_test_dll_offset()
10334 if (mode == DBTRAIN_TEST) { in hw_assist_test_dll_offset()
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/ram/octeon/
H A Docteon3_lmc.c72 #define DBTRAIN_TEST 0 macro
5364 DBTRAIN_TEST, bad_bits); in lmc_sw_write_leveling_loop()
5604 DBTRAIN_TEST, in parallel_wl_block_delay()
6027 DBTRAIN_TEST, in lmc_sw_write_leveling()
10215 case DBTRAIN_TEST: // always choose LFSR if chip supports it in choose_best_hw_patterns()
10236 new_mode = DBTRAIN_TEST; in choose_best_hw_patterns()
10305 int mode = choose_best_hw_patterns(lmc, DBTRAIN_TEST); in hw_assist_test_dll_offset()
10334 if (mode == DBTRAIN_TEST) { in hw_assist_test_dll_offset()
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/ram/octeon/
H A Docteon3_lmc.c72 #define DBTRAIN_TEST 0 macro
5364 DBTRAIN_TEST, bad_bits); in lmc_sw_write_leveling_loop()
5604 DBTRAIN_TEST, in parallel_wl_block_delay()
6027 DBTRAIN_TEST, in lmc_sw_write_leveling()
10215 case DBTRAIN_TEST: // always choose LFSR if chip supports it in choose_best_hw_patterns()
10236 new_mode = DBTRAIN_TEST; in choose_best_hw_patterns()
10305 int mode = choose_best_hw_patterns(lmc, DBTRAIN_TEST); in hw_assist_test_dll_offset()
10334 if (mode == DBTRAIN_TEST) { in hw_assist_test_dll_offset()
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/ram/octeon/
H A Docteon3_lmc.c72 #define DBTRAIN_TEST 0 macro
5364 DBTRAIN_TEST, bad_bits); in lmc_sw_write_leveling_loop()
5604 DBTRAIN_TEST, in parallel_wl_block_delay()
6027 DBTRAIN_TEST, in lmc_sw_write_leveling()
10215 case DBTRAIN_TEST: // always choose LFSR if chip supports it in choose_best_hw_patterns()
10236 new_mode = DBTRAIN_TEST; in choose_best_hw_patterns()
10305 int mode = choose_best_hw_patterns(lmc, DBTRAIN_TEST); in hw_assist_test_dll_offset()
10334 if (mode == DBTRAIN_TEST) { in hw_assist_test_dll_offset()
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/ram/octeon/
H A Docteon3_lmc.c72 #define DBTRAIN_TEST 0 macro
5364 DBTRAIN_TEST, bad_bits); in lmc_sw_write_leveling_loop()
5604 DBTRAIN_TEST, in parallel_wl_block_delay()
6027 DBTRAIN_TEST, in lmc_sw_write_leveling()
10215 case DBTRAIN_TEST: // always choose LFSR if chip supports it in choose_best_hw_patterns()
10236 new_mode = DBTRAIN_TEST; in choose_best_hw_patterns()
10305 int mode = choose_best_hw_patterns(lmc, DBTRAIN_TEST); in hw_assist_test_dll_offset()
10334 if (mode == DBTRAIN_TEST) { in hw_assist_test_dll_offset()
/dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/ram/octeon/
H A Docteon3_lmc.c72 #define DBTRAIN_TEST 0 macro
5364 DBTRAIN_TEST, bad_bits); in lmc_sw_write_leveling_loop()
5604 DBTRAIN_TEST, in parallel_wl_block_delay()
6027 DBTRAIN_TEST, in lmc_sw_write_leveling()
10215 case DBTRAIN_TEST: // always choose LFSR if chip supports it in choose_best_hw_patterns()
10236 new_mode = DBTRAIN_TEST; in choose_best_hw_patterns()
10305 int mode = choose_best_hw_patterns(lmc, DBTRAIN_TEST); in hw_assist_test_dll_offset()
10334 if (mode == DBTRAIN_TEST) { in hw_assist_test_dll_offset()
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/ram/octeon/
H A Docteon3_lmc.c72 #define DBTRAIN_TEST 0 macro
5364 DBTRAIN_TEST, bad_bits); in lmc_sw_write_leveling_loop()
5604 DBTRAIN_TEST, in parallel_wl_block_delay()
6027 DBTRAIN_TEST, in lmc_sw_write_leveling()
10215 case DBTRAIN_TEST: // always choose LFSR if chip supports it in choose_best_hw_patterns()
10236 new_mode = DBTRAIN_TEST; in choose_best_hw_patterns()
10305 int mode = choose_best_hw_patterns(lmc, DBTRAIN_TEST); in hw_assist_test_dll_offset()
10334 if (mode == DBTRAIN_TEST) { in hw_assist_test_dll_offset()
/dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/ram/octeon/
H A Docteon3_lmc.c72 #define DBTRAIN_TEST 0 macro
5364 DBTRAIN_TEST, bad_bits); in lmc_sw_write_leveling_loop()
5604 DBTRAIN_TEST, in parallel_wl_block_delay()
6027 DBTRAIN_TEST, in lmc_sw_write_leveling()
10215 case DBTRAIN_TEST: // always choose LFSR if chip supports it in choose_best_hw_patterns()
10236 new_mode = DBTRAIN_TEST; in choose_best_hw_patterns()
10305 int mode = choose_best_hw_patterns(lmc, DBTRAIN_TEST); in hw_assist_test_dll_offset()
10334 if (mode == DBTRAIN_TEST) { in hw_assist_test_dll_offset()
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/ram/octeon/
H A Docteon3_lmc.c72 #define DBTRAIN_TEST 0 macro
5364 DBTRAIN_TEST, bad_bits); in lmc_sw_write_leveling_loop()
5604 DBTRAIN_TEST, in parallel_wl_block_delay()
6027 DBTRAIN_TEST, in lmc_sw_write_leveling()
10215 case DBTRAIN_TEST: // always choose LFSR if chip supports it in choose_best_hw_patterns()
10236 new_mode = DBTRAIN_TEST; in choose_best_hw_patterns()
10305 int mode = choose_best_hw_patterns(lmc, DBTRAIN_TEST); in hw_assist_test_dll_offset()
10334 if (mode == DBTRAIN_TEST) { in hw_assist_test_dll_offset()
/dports/sysutils/u-boot-pinebookpro/u-boot-2021.07/drivers/ram/octeon/
H A Docteon3_lmc.c72 #define DBTRAIN_TEST 0 macro
5364 DBTRAIN_TEST, bad_bits); in lmc_sw_write_leveling_loop()
5604 DBTRAIN_TEST, in parallel_wl_block_delay()
6027 DBTRAIN_TEST, in lmc_sw_write_leveling()
10215 case DBTRAIN_TEST: // always choose LFSR if chip supports it in choose_best_hw_patterns()
10236 new_mode = DBTRAIN_TEST; in choose_best_hw_patterns()
10305 int mode = choose_best_hw_patterns(lmc, DBTRAIN_TEST); in hw_assist_test_dll_offset()
10334 if (mode == DBTRAIN_TEST) { in hw_assist_test_dll_offset()
/dports/sysutils/u-boot-nanopi-neo2/u-boot-2021.07/drivers/ram/octeon/
H A Docteon3_lmc.c72 #define DBTRAIN_TEST 0 macro
5364 DBTRAIN_TEST, bad_bits); in lmc_sw_write_leveling_loop()
5604 DBTRAIN_TEST, in parallel_wl_block_delay()
6027 DBTRAIN_TEST, in lmc_sw_write_leveling()
10215 case DBTRAIN_TEST: // always choose LFSR if chip supports it in choose_best_hw_patterns()
10236 new_mode = DBTRAIN_TEST; in choose_best_hw_patterns()
10305 int mode = choose_best_hw_patterns(lmc, DBTRAIN_TEST); in hw_assist_test_dll_offset()
10334 if (mode == DBTRAIN_TEST) { in hw_assist_test_dll_offset()
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/ram/octeon/
H A Docteon3_lmc.c72 #define DBTRAIN_TEST 0 macro
5364 DBTRAIN_TEST, bad_bits); in lmc_sw_write_leveling_loop()
5604 DBTRAIN_TEST, in parallel_wl_block_delay()
6027 DBTRAIN_TEST, in lmc_sw_write_leveling()
10215 case DBTRAIN_TEST: // always choose LFSR if chip supports it in choose_best_hw_patterns()
10236 new_mode = DBTRAIN_TEST; in choose_best_hw_patterns()
10305 int mode = choose_best_hw_patterns(lmc, DBTRAIN_TEST); in hw_assist_test_dll_offset()
10334 if (mode == DBTRAIN_TEST) { in hw_assist_test_dll_offset()
/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/ram/octeon/
H A Docteon3_lmc.c72 #define DBTRAIN_TEST 0 macro
5364 DBTRAIN_TEST, bad_bits); in lmc_sw_write_leveling_loop()
5604 DBTRAIN_TEST, in parallel_wl_block_delay()
6027 DBTRAIN_TEST, in lmc_sw_write_leveling()
10215 case DBTRAIN_TEST: // always choose LFSR if chip supports it in choose_best_hw_patterns()
10236 new_mode = DBTRAIN_TEST; in choose_best_hw_patterns()
10305 int mode = choose_best_hw_patterns(lmc, DBTRAIN_TEST); in hw_assist_test_dll_offset()
10334 if (mode == DBTRAIN_TEST) { in hw_assist_test_dll_offset()
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/ram/octeon/
H A Docteon3_lmc.c72 #define DBTRAIN_TEST 0 macro
5364 DBTRAIN_TEST, bad_bits); in lmc_sw_write_leveling_loop()
5604 DBTRAIN_TEST, in parallel_wl_block_delay()
6027 DBTRAIN_TEST, in lmc_sw_write_leveling()
10215 case DBTRAIN_TEST: // always choose LFSR if chip supports it in choose_best_hw_patterns()
10236 new_mode = DBTRAIN_TEST; in choose_best_hw_patterns()
10305 int mode = choose_best_hw_patterns(lmc, DBTRAIN_TEST); in hw_assist_test_dll_offset()
10334 if (mode == DBTRAIN_TEST) { in hw_assist_test_dll_offset()
/dports/sysutils/u-boot-beaglebone/u-boot-2021.07/drivers/ram/octeon/
H A Docteon3_lmc.c72 #define DBTRAIN_TEST 0 macro
5364 DBTRAIN_TEST, bad_bits); in lmc_sw_write_leveling_loop()
5604 DBTRAIN_TEST, in parallel_wl_block_delay()
6027 DBTRAIN_TEST, in lmc_sw_write_leveling()
10215 case DBTRAIN_TEST: // always choose LFSR if chip supports it in choose_best_hw_patterns()
10236 new_mode = DBTRAIN_TEST; in choose_best_hw_patterns()
10305 int mode = choose_best_hw_patterns(lmc, DBTRAIN_TEST); in hw_assist_test_dll_offset()
10334 if (mode == DBTRAIN_TEST) { in hw_assist_test_dll_offset()
/dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/ram/octeon/
H A Docteon3_lmc.c72 #define DBTRAIN_TEST 0 macro
5364 DBTRAIN_TEST, bad_bits); in lmc_sw_write_leveling_loop()
5604 DBTRAIN_TEST, in parallel_wl_block_delay()
6027 DBTRAIN_TEST, in lmc_sw_write_leveling()
10215 case DBTRAIN_TEST: // always choose LFSR if chip supports it in choose_best_hw_patterns()
10236 new_mode = DBTRAIN_TEST; in choose_best_hw_patterns()
10305 int mode = choose_best_hw_patterns(lmc, DBTRAIN_TEST); in hw_assist_test_dll_offset()
10334 if (mode == DBTRAIN_TEST) { in hw_assist_test_dll_offset()
/dports/sysutils/u-boot-clearfog/u-boot-2021.07/drivers/ram/octeon/
H A Docteon3_lmc.c72 #define DBTRAIN_TEST 0 macro
5364 DBTRAIN_TEST, bad_bits); in lmc_sw_write_leveling_loop()
5604 DBTRAIN_TEST, in parallel_wl_block_delay()
6027 DBTRAIN_TEST, in lmc_sw_write_leveling()
10215 case DBTRAIN_TEST: // always choose LFSR if chip supports it in choose_best_hw_patterns()
10236 new_mode = DBTRAIN_TEST; in choose_best_hw_patterns()
10305 int mode = choose_best_hw_patterns(lmc, DBTRAIN_TEST); in hw_assist_test_dll_offset()
10334 if (mode == DBTRAIN_TEST) { in hw_assist_test_dll_offset()
/dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/drivers/ram/octeon/
H A Docteon3_lmc.c72 #define DBTRAIN_TEST 0 macro
5364 DBTRAIN_TEST, bad_bits); in lmc_sw_write_leveling_loop()
5604 DBTRAIN_TEST, in parallel_wl_block_delay()
6027 DBTRAIN_TEST, in lmc_sw_write_leveling()
10215 case DBTRAIN_TEST: // always choose LFSR if chip supports it in choose_best_hw_patterns()
10236 new_mode = DBTRAIN_TEST; in choose_best_hw_patterns()
10305 int mode = choose_best_hw_patterns(lmc, DBTRAIN_TEST); in hw_assist_test_dll_offset()
10334 if (mode == DBTRAIN_TEST) { in hw_assist_test_dll_offset()
/dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/drivers/ram/octeon/
H A Docteon3_lmc.c72 #define DBTRAIN_TEST 0 macro
5364 DBTRAIN_TEST, bad_bits); in lmc_sw_write_leveling_loop()
5604 DBTRAIN_TEST, in parallel_wl_block_delay()
6027 DBTRAIN_TEST, in lmc_sw_write_leveling()
10215 case DBTRAIN_TEST: // always choose LFSR if chip supports it in choose_best_hw_patterns()
10236 new_mode = DBTRAIN_TEST; in choose_best_hw_patterns()
10305 int mode = choose_best_hw_patterns(lmc, DBTRAIN_TEST); in hw_assist_test_dll_offset()
10334 if (mode == DBTRAIN_TEST) { in hw_assist_test_dll_offset()
/dports/sysutils/u-boot-pandaboard/u-boot-2021.07/drivers/ram/octeon/
H A Docteon3_lmc.c72 #define DBTRAIN_TEST 0 macro
5364 DBTRAIN_TEST, bad_bits); in lmc_sw_write_leveling_loop()
5604 DBTRAIN_TEST, in parallel_wl_block_delay()
6027 DBTRAIN_TEST, in lmc_sw_write_leveling()
10215 case DBTRAIN_TEST: // always choose LFSR if chip supports it in choose_best_hw_patterns()
10236 new_mode = DBTRAIN_TEST; in choose_best_hw_patterns()
10305 int mode = choose_best_hw_patterns(lmc, DBTRAIN_TEST); in hw_assist_test_dll_offset()
10334 if (mode == DBTRAIN_TEST) { in hw_assist_test_dll_offset()
/dports/sysutils/u-boot-orangepi-r1/u-boot-2021.07/drivers/ram/octeon/
H A Docteon3_lmc.c72 #define DBTRAIN_TEST 0 macro
5364 DBTRAIN_TEST, bad_bits); in lmc_sw_write_leveling_loop()
5604 DBTRAIN_TEST, in parallel_wl_block_delay()
6027 DBTRAIN_TEST, in lmc_sw_write_leveling()
10215 case DBTRAIN_TEST: // always choose LFSR if chip supports it in choose_best_hw_patterns()
10236 new_mode = DBTRAIN_TEST; in choose_best_hw_patterns()
10305 int mode = choose_best_hw_patterns(lmc, DBTRAIN_TEST); in hw_assist_test_dll_offset()
10334 if (mode == DBTRAIN_TEST) { in hw_assist_test_dll_offset()
/dports/sysutils/u-boot-pine-h64/u-boot-2021.07/drivers/ram/octeon/
H A Docteon3_lmc.c72 #define DBTRAIN_TEST 0
5364 DBTRAIN_TEST, bad_bits);
5604 DBTRAIN_TEST,
6027 DBTRAIN_TEST,
10215 case DBTRAIN_TEST: // always choose LFSR if chip supports it
10236 new_mode = DBTRAIN_TEST;
10305 int mode = choose_best_hw_patterns(lmc, DBTRAIN_TEST);
10334 if (mode == DBTRAIN_TEST) {

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