Home
last modified time | relevance | path

Searched refs:DCMD_FLOWSRC (Results 1 – 25 of 84) sorted by relevance

1234

/dports/emulators/qemu42/qemu-4.2.1/hw/dma/
H A Dpxa2xx_dma.c96 #define DCMD_FLOWSRC (1 << 29) macro
170 if (s->chan[ch].cmd & DCMD_FLOWSRC) in pxa2xx_dma_descriptor_fetch()
201 if ((ch->cmd & (DCMD_FLOWSRC | DCMD_FLOWTRG)) && !ch->request) in pxa2xx_dma_run()
226 if ((ch->cmd & (DCMD_FLOWSRC | DCMD_FLOWTRG)) && in pxa2xx_dma_run()
/dports/emulators/qemu/qemu-6.2.0/hw/dma/
H A Dpxa2xx_dma.c98 #define DCMD_FLOWSRC (1 << 29) macro
172 if (s->chan[ch].cmd & DCMD_FLOWSRC) in pxa2xx_dma_descriptor_fetch()
203 if ((ch->cmd & (DCMD_FLOWSRC | DCMD_FLOWTRG)) && !ch->request) in pxa2xx_dma_run()
228 if ((ch->cmd & (DCMD_FLOWSRC | DCMD_FLOWTRG)) && in pxa2xx_dma_run()
/dports/emulators/qemu60/qemu-6.0.0/hw/dma/
H A Dpxa2xx_dma.c98 #define DCMD_FLOWSRC (1 << 29) macro
172 if (s->chan[ch].cmd & DCMD_FLOWSRC) in pxa2xx_dma_descriptor_fetch()
203 if ((ch->cmd & (DCMD_FLOWSRC | DCMD_FLOWTRG)) && !ch->request) in pxa2xx_dma_run()
228 if ((ch->cmd & (DCMD_FLOWSRC | DCMD_FLOWTRG)) && in pxa2xx_dma_run()
/dports/emulators/qemu-utils/qemu-4.2.1/hw/dma/
H A Dpxa2xx_dma.c96 #define DCMD_FLOWSRC (1 << 29) macro
170 if (s->chan[ch].cmd & DCMD_FLOWSRC) in pxa2xx_dma_descriptor_fetch()
201 if ((ch->cmd & (DCMD_FLOWSRC | DCMD_FLOWTRG)) && !ch->request) in pxa2xx_dma_run()
226 if ((ch->cmd & (DCMD_FLOWSRC | DCMD_FLOWTRG)) && in pxa2xx_dma_run()
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/hw/dma/
H A Dpxa2xx_dma.c92 #define DCMD_FLOWSRC (1 << 29) macro
166 if (s->chan[ch].cmd & DCMD_FLOWSRC) in pxa2xx_dma_descriptor_fetch()
197 if ((ch->cmd & (DCMD_FLOWSRC | DCMD_FLOWTRG)) && !ch->request) in pxa2xx_dma_run()
222 if ((ch->cmd & (DCMD_FLOWSRC | DCMD_FLOWTRG)) && in pxa2xx_dma_run()
/dports/emulators/qemu5/qemu-5.2.0/hw/dma/
H A Dpxa2xx_dma.c98 #define DCMD_FLOWSRC (1 << 29) macro
172 if (s->chan[ch].cmd & DCMD_FLOWSRC) in pxa2xx_dma_descriptor_fetch()
203 if ((ch->cmd & (DCMD_FLOWSRC | DCMD_FLOWTRG)) && !ch->request) in pxa2xx_dma_run()
228 if ((ch->cmd & (DCMD_FLOWSRC | DCMD_FLOWTRG)) && in pxa2xx_dma_run()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/hw/dma/
H A Dpxa2xx_dma.c96 #define DCMD_FLOWSRC (1 << 29) macro
170 if (s->chan[ch].cmd & DCMD_FLOWSRC) in pxa2xx_dma_descriptor_fetch()
201 if ((ch->cmd & (DCMD_FLOWSRC | DCMD_FLOWTRG)) && !ch->request) in pxa2xx_dma_run()
226 if ((ch->cmd & (DCMD_FLOWSRC | DCMD_FLOWTRG)) && in pxa2xx_dma_run()
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/hw/dma/
H A Dpxa2xx_dma.c96 #define DCMD_FLOWSRC (1 << 29) macro
170 if (s->chan[ch].cmd & DCMD_FLOWSRC) in pxa2xx_dma_descriptor_fetch()
201 if ((ch->cmd & (DCMD_FLOWSRC | DCMD_FLOWTRG)) && !ch->request) in pxa2xx_dma_run()
226 if ((ch->cmd & (DCMD_FLOWSRC | DCMD_FLOWTRG)) && in pxa2xx_dma_run()
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/hw/dma/
H A Dpxa2xx_dma.c98 #define DCMD_FLOWSRC (1 << 29) macro
172 if (s->chan[ch].cmd & DCMD_FLOWSRC) in pxa2xx_dma_descriptor_fetch()
203 if ((ch->cmd & (DCMD_FLOWSRC | DCMD_FLOWTRG)) && !ch->request) in pxa2xx_dma_run()
228 if ((ch->cmd & (DCMD_FLOWSRC | DCMD_FLOWTRG)) && in pxa2xx_dma_run()
/dports/devel/openwince-include/include-0.4.2/arm/pxa2x0/
H A Ddma.h249 #define DCMD_FLOWSRC bit(29) macro
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h298 #define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */ macro
312 #define DCMD_RXPCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
313 #define DCMD_RXMCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
/dports/emulators/qemu/qemu-6.2.0/roms/u-boot/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h298 #define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */ macro
312 #define DCMD_RXPCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
313 #define DCMD_RXMCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h298 #define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */ macro
312 #define DCMD_RXPCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
313 #define DCMD_RXMCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h298 #define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */ macro
312 #define DCMD_RXPCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
313 #define DCMD_RXMCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h298 #define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */ macro
312 #define DCMD_RXPCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
313 #define DCMD_RXMCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h298 #define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */ macro
312 #define DCMD_RXPCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
313 #define DCMD_RXMCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h298 #define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */ macro
312 #define DCMD_RXPCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
313 #define DCMD_RXMCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h298 #define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */ macro
312 #define DCMD_RXPCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
313 #define DCMD_RXMCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h298 #define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */ macro
312 #define DCMD_RXPCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
313 #define DCMD_RXMCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h298 #define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */ macro
312 #define DCMD_RXPCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
313 #define DCMD_RXMCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
/dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h298 #define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */ macro
312 #define DCMD_RXPCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
313 #define DCMD_RXMCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
/dports/sysutils/u-boot-bananapi/u-boot-2021.07/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h298 #define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */ macro
312 #define DCMD_RXPCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
313 #define DCMD_RXMCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
/dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h298 #define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */ macro
312 #define DCMD_RXPCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
313 #define DCMD_RXMCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h298 #define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */ macro
312 #define DCMD_RXPCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
313 #define DCMD_RXMCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
/dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h298 #define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */ macro
312 #define DCMD_RXPCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
313 #define DCMD_RXMCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)

1234