/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/drivers/ddr/marvell/axp/ |
H A D | ddr3_read_leveling.c | 19 DEBUG_RL_S(s); DEBUG_RL_D(d, l); DEBUG_RL_S("\n") 26 #define DEBUG_RL_D(d, l) \ macro 30 #define DEBUG_RL_D(d, l) macro 137 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_hw() 139 DEBUG_RL_D((u32) dram_info-> in ddr3_read_leveling_hw() 142 DEBUG_RL_D((u32) dram_info-> in ddr3_read_leveling_hw() 269 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_sw() 271 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][P], 1); in ddr3_read_leveling_sw() 273 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][D], 2); in ddr3_read_leveling_sw() 1093 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_single_cs_window_mode() [all …]
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/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/drivers/ddr/marvell/axp/ |
H A D | ddr3_read_leveling.c | 19 DEBUG_RL_S(s); DEBUG_RL_D(d, l); DEBUG_RL_S("\n") 26 #define DEBUG_RL_D(d, l) \ macro 30 #define DEBUG_RL_D(d, l) macro 137 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_hw() 139 DEBUG_RL_D((u32) dram_info-> in ddr3_read_leveling_hw() 142 DEBUG_RL_D((u32) dram_info-> in ddr3_read_leveling_hw() 269 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_sw() 271 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][P], 1); in ddr3_read_leveling_sw() 273 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][D], 2); in ddr3_read_leveling_sw() 1093 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_single_cs_window_mode() [all …]
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/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/ddr/marvell/axp/ |
H A D | ddr3_read_leveling.c | 20 DEBUG_RL_S(s); DEBUG_RL_D(d, l); DEBUG_RL_S("\n") 27 #define DEBUG_RL_D(d, l) \ macro 31 #define DEBUG_RL_D(d, l) macro 138 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_hw() 140 DEBUG_RL_D((u32) dram_info-> in ddr3_read_leveling_hw() 143 DEBUG_RL_D((u32) dram_info-> in ddr3_read_leveling_hw() 270 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_sw() 272 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][P], 1); in ddr3_read_leveling_sw() 274 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][D], 2); in ddr3_read_leveling_sw() 1094 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_single_cs_window_mode() [all …]
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/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/ddr/marvell/axp/ |
H A D | ddr3_read_leveling.c | 20 DEBUG_RL_S(s); DEBUG_RL_D(d, l); DEBUG_RL_S("\n") 27 #define DEBUG_RL_D(d, l) \ macro 31 #define DEBUG_RL_D(d, l) macro 138 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_hw() 140 DEBUG_RL_D((u32) dram_info-> in ddr3_read_leveling_hw() 143 DEBUG_RL_D((u32) dram_info-> in ddr3_read_leveling_hw() 270 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_sw() 272 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][P], 1); in ddr3_read_leveling_sw() 274 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][D], 2); in ddr3_read_leveling_sw() 1094 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_single_cs_window_mode() [all …]
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/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/ddr/marvell/axp/ |
H A D | ddr3_read_leveling.c | 20 DEBUG_RL_S(s); DEBUG_RL_D(d, l); DEBUG_RL_S("\n") 27 #define DEBUG_RL_D(d, l) \ macro 31 #define DEBUG_RL_D(d, l) macro 138 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_hw() 140 DEBUG_RL_D((u32) dram_info-> in ddr3_read_leveling_hw() 143 DEBUG_RL_D((u32) dram_info-> in ddr3_read_leveling_hw() 270 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_sw() 272 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][P], 1); in ddr3_read_leveling_sw() 274 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][D], 2); in ddr3_read_leveling_sw() 1094 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_single_cs_window_mode() [all …]
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/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/drivers/ddr/marvell/axp/ |
H A D | ddr3_read_leveling.c | 20 DEBUG_RL_S(s); DEBUG_RL_D(d, l); DEBUG_RL_S("\n") 27 #define DEBUG_RL_D(d, l) \ macro 31 #define DEBUG_RL_D(d, l) macro 138 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_hw() 140 DEBUG_RL_D((u32) dram_info-> in ddr3_read_leveling_hw() 143 DEBUG_RL_D((u32) dram_info-> in ddr3_read_leveling_hw() 270 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_sw() 272 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][P], 1); in ddr3_read_leveling_sw() 274 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][D], 2); in ddr3_read_leveling_sw() 1094 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_single_cs_window_mode() [all …]
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/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/ddr/marvell/axp/ |
H A D | ddr3_read_leveling.c | 20 DEBUG_RL_S(s); DEBUG_RL_D(d, l); DEBUG_RL_S("\n") 27 #define DEBUG_RL_D(d, l) \ macro 31 #define DEBUG_RL_D(d, l) macro 138 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_hw() 140 DEBUG_RL_D((u32) dram_info-> in ddr3_read_leveling_hw() 143 DEBUG_RL_D((u32) dram_info-> in ddr3_read_leveling_hw() 270 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_sw() 272 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][P], 1); in ddr3_read_leveling_sw() 274 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][D], 2); in ddr3_read_leveling_sw() 1094 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_single_cs_window_mode() [all …]
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/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/ddr/marvell/axp/ |
H A D | ddr3_read_leveling.c | 20 DEBUG_RL_S(s); DEBUG_RL_D(d, l); DEBUG_RL_S("\n") 27 #define DEBUG_RL_D(d, l) \ macro 31 #define DEBUG_RL_D(d, l) macro 138 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_hw() 140 DEBUG_RL_D((u32) dram_info-> in ddr3_read_leveling_hw() 143 DEBUG_RL_D((u32) dram_info-> in ddr3_read_leveling_hw() 270 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_sw() 272 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][P], 1); in ddr3_read_leveling_sw() 274 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][D], 2); in ddr3_read_leveling_sw() 1094 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_single_cs_window_mode() [all …]
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/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/ddr/marvell/axp/ |
H A D | ddr3_read_leveling.c | 20 DEBUG_RL_S(s); DEBUG_RL_D(d, l); DEBUG_RL_S("\n") 27 #define DEBUG_RL_D(d, l) \ macro 31 #define DEBUG_RL_D(d, l) macro 138 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_hw() 140 DEBUG_RL_D((u32) dram_info-> in ddr3_read_leveling_hw() 143 DEBUG_RL_D((u32) dram_info-> in ddr3_read_leveling_hw() 270 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_sw() 272 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][P], 1); in ddr3_read_leveling_sw() 274 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][D], 2); in ddr3_read_leveling_sw() 1094 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_single_cs_window_mode() [all …]
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/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/ddr/marvell/axp/ |
H A D | ddr3_read_leveling.c | 20 DEBUG_RL_S(s); DEBUG_RL_D(d, l); DEBUG_RL_S("\n") 27 #define DEBUG_RL_D(d, l) \ macro 31 #define DEBUG_RL_D(d, l) macro 138 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_hw() 140 DEBUG_RL_D((u32) dram_info-> in ddr3_read_leveling_hw() 143 DEBUG_RL_D((u32) dram_info-> in ddr3_read_leveling_hw() 270 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_sw() 272 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][P], 1); in ddr3_read_leveling_sw() 274 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][D], 2); in ddr3_read_leveling_sw() 1094 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_single_cs_window_mode() [all …]
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/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/ddr/marvell/axp/ |
H A D | ddr3_read_leveling.c | 20 DEBUG_RL_S(s); DEBUG_RL_D(d, l); DEBUG_RL_S("\n") 27 #define DEBUG_RL_D(d, l) \ macro 31 #define DEBUG_RL_D(d, l) macro 138 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_hw() 140 DEBUG_RL_D((u32) dram_info-> in ddr3_read_leveling_hw() 143 DEBUG_RL_D((u32) dram_info-> in ddr3_read_leveling_hw() 270 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_sw() 272 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][P], 1); in ddr3_read_leveling_sw() 274 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][D], 2); in ddr3_read_leveling_sw() 1094 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_single_cs_window_mode() [all …]
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/dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/ddr/marvell/axp/ |
H A D | ddr3_read_leveling.c | 20 DEBUG_RL_S(s); DEBUG_RL_D(d, l); DEBUG_RL_S("\n") 27 #define DEBUG_RL_D(d, l) \ macro 31 #define DEBUG_RL_D(d, l) macro 138 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_hw() 140 DEBUG_RL_D((u32) dram_info-> in ddr3_read_leveling_hw() 143 DEBUG_RL_D((u32) dram_info-> in ddr3_read_leveling_hw() 270 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_sw() 272 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][P], 1); in ddr3_read_leveling_sw() 274 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][D], 2); in ddr3_read_leveling_sw() 1094 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_single_cs_window_mode() [all …]
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/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/ddr/marvell/axp/ |
H A D | ddr3_read_leveling.c | 20 DEBUG_RL_S(s); DEBUG_RL_D(d, l); DEBUG_RL_S("\n") 27 #define DEBUG_RL_D(d, l) \ macro 31 #define DEBUG_RL_D(d, l) macro 138 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_hw() 140 DEBUG_RL_D((u32) dram_info-> in ddr3_read_leveling_hw() 143 DEBUG_RL_D((u32) dram_info-> in ddr3_read_leveling_hw() 270 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_sw() 272 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][P], 1); in ddr3_read_leveling_sw() 274 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][D], 2); in ddr3_read_leveling_sw() 1094 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_single_cs_window_mode() [all …]
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/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/ddr/marvell/axp/ |
H A D | ddr3_read_leveling.c | 20 DEBUG_RL_S(s); DEBUG_RL_D(d, l); DEBUG_RL_S("\n") 27 #define DEBUG_RL_D(d, l) \ macro 31 #define DEBUG_RL_D(d, l) macro 138 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_hw() 140 DEBUG_RL_D((u32) dram_info-> in ddr3_read_leveling_hw() 143 DEBUG_RL_D((u32) dram_info-> in ddr3_read_leveling_hw() 270 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_sw() 272 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][P], 1); in ddr3_read_leveling_sw() 274 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][D], 2); in ddr3_read_leveling_sw() 1094 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_single_cs_window_mode() [all …]
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/dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/ddr/marvell/axp/ |
H A D | ddr3_read_leveling.c | 20 DEBUG_RL_S(s); DEBUG_RL_D(d, l); DEBUG_RL_S("\n") 27 #define DEBUG_RL_D(d, l) \ macro 31 #define DEBUG_RL_D(d, l) macro 138 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_hw() 140 DEBUG_RL_D((u32) dram_info-> in ddr3_read_leveling_hw() 143 DEBUG_RL_D((u32) dram_info-> in ddr3_read_leveling_hw() 270 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_sw() 272 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][P], 1); in ddr3_read_leveling_sw() 274 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][D], 2); in ddr3_read_leveling_sw() 1094 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_single_cs_window_mode() [all …]
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/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/ddr/marvell/axp/ |
H A D | ddr3_read_leveling.c | 20 DEBUG_RL_S(s); DEBUG_RL_D(d, l); DEBUG_RL_S("\n") 27 #define DEBUG_RL_D(d, l) \ macro 31 #define DEBUG_RL_D(d, l) macro 138 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_hw() 140 DEBUG_RL_D((u32) dram_info-> in ddr3_read_leveling_hw() 143 DEBUG_RL_D((u32) dram_info-> in ddr3_read_leveling_hw() 270 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_sw() 272 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][P], 1); in ddr3_read_leveling_sw() 274 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][D], 2); in ddr3_read_leveling_sw() 1094 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_single_cs_window_mode() [all …]
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/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/ddr/marvell/axp/ |
H A D | ddr3_read_leveling.c | 20 DEBUG_RL_S(s); DEBUG_RL_D(d, l); DEBUG_RL_S("\n") 27 #define DEBUG_RL_D(d, l) \ macro 31 #define DEBUG_RL_D(d, l) macro 138 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_hw() 140 DEBUG_RL_D((u32) dram_info-> in ddr3_read_leveling_hw() 143 DEBUG_RL_D((u32) dram_info-> in ddr3_read_leveling_hw() 270 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_sw() 272 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][P], 1); in ddr3_read_leveling_sw() 274 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][D], 2); in ddr3_read_leveling_sw() 1094 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_single_cs_window_mode() [all …]
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/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/drivers/ddr/marvell/axp/ |
H A D | ddr3_read_leveling.c | 20 DEBUG_RL_S(s); DEBUG_RL_D(d, l); DEBUG_RL_S("\n") 27 #define DEBUG_RL_D(d, l) \ macro 31 #define DEBUG_RL_D(d, l) macro 138 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_hw() 140 DEBUG_RL_D((u32) dram_info-> in ddr3_read_leveling_hw() 143 DEBUG_RL_D((u32) dram_info-> in ddr3_read_leveling_hw() 270 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_sw() 272 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][P], 1); in ddr3_read_leveling_sw() 274 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][D], 2); in ddr3_read_leveling_sw() 1094 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_single_cs_window_mode() [all …]
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/dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/ddr/marvell/axp/ |
H A D | ddr3_read_leveling.c | 20 DEBUG_RL_S(s); DEBUG_RL_D(d, l); DEBUG_RL_S("\n") 27 #define DEBUG_RL_D(d, l) \ macro 31 #define DEBUG_RL_D(d, l) macro 138 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_hw() 140 DEBUG_RL_D((u32) dram_info-> in ddr3_read_leveling_hw() 143 DEBUG_RL_D((u32) dram_info-> in ddr3_read_leveling_hw() 270 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_sw() 272 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][P], 1); in ddr3_read_leveling_sw() 274 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][D], 2); in ddr3_read_leveling_sw() 1094 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_single_cs_window_mode() [all …]
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/dports/sysutils/u-boot-wandboard/u-boot-2021.07/drivers/ddr/marvell/axp/ |
H A D | ddr3_read_leveling.c | 20 DEBUG_RL_S(s); DEBUG_RL_D(d, l); DEBUG_RL_S("\n") 27 #define DEBUG_RL_D(d, l) \ macro 31 #define DEBUG_RL_D(d, l) macro 138 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_hw() 140 DEBUG_RL_D((u32) dram_info-> in ddr3_read_leveling_hw() 143 DEBUG_RL_D((u32) dram_info-> in ddr3_read_leveling_hw() 270 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_sw() 272 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][P], 1); in ddr3_read_leveling_sw() 274 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][D], 2); in ddr3_read_leveling_sw() 1094 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_single_cs_window_mode() [all …]
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/dports/sysutils/u-boot-beaglebone/u-boot-2021.07/drivers/ddr/marvell/axp/ |
H A D | ddr3_read_leveling.c | 20 DEBUG_RL_S(s); DEBUG_RL_D(d, l); DEBUG_RL_S("\n") 27 #define DEBUG_RL_D(d, l) \ macro 31 #define DEBUG_RL_D(d, l) macro 138 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_hw() 140 DEBUG_RL_D((u32) dram_info-> in ddr3_read_leveling_hw() 143 DEBUG_RL_D((u32) dram_info-> in ddr3_read_leveling_hw() 270 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_sw() 272 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][P], 1); in ddr3_read_leveling_sw() 274 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][D], 2); in ddr3_read_leveling_sw() 1094 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_single_cs_window_mode() [all …]
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/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/drivers/ddr/marvell/axp/ |
H A D | ddr3_read_leveling.c | 19 DEBUG_RL_S(s); DEBUG_RL_D(d, l); DEBUG_RL_S("\n") 26 #define DEBUG_RL_D(d, l) \ macro 30 #define DEBUG_RL_D(d, l) macro 137 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_hw() 139 DEBUG_RL_D((u32) dram_info-> in ddr3_read_leveling_hw() 142 DEBUG_RL_D((u32) dram_info-> in ddr3_read_leveling_hw() 269 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_sw() 271 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][P], 1); in ddr3_read_leveling_sw() 273 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][D], 2); in ddr3_read_leveling_sw() 1093 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_single_cs_window_mode() [all …]
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/drivers/ddr/marvell/axp/ |
H A D | ddr3_read_leveling.c | 19 DEBUG_RL_S(s); DEBUG_RL_D(d, l); DEBUG_RL_S("\n") 26 #define DEBUG_RL_D(d, l) \ macro 30 #define DEBUG_RL_D(d, l) macro 137 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_hw() 139 DEBUG_RL_D((u32) dram_info-> in ddr3_read_leveling_hw() 142 DEBUG_RL_D((u32) dram_info-> in ddr3_read_leveling_hw() 269 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_sw() 271 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][P], 1); in ddr3_read_leveling_sw() 273 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][D], 2); in ddr3_read_leveling_sw() 1093 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_single_cs_window_mode() [all …]
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/dports/sysutils/u-boot-clearfog/u-boot-2021.07/drivers/ddr/marvell/axp/ |
H A D | ddr3_read_leveling.c | 20 DEBUG_RL_S(s); DEBUG_RL_D(d, l); DEBUG_RL_S("\n") 27 #define DEBUG_RL_D(d, l) \ macro 31 #define DEBUG_RL_D(d, l) macro 138 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_hw() 140 DEBUG_RL_D((u32) dram_info-> in ddr3_read_leveling_hw() 143 DEBUG_RL_D((u32) dram_info-> in ddr3_read_leveling_hw() 270 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_sw() 272 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][P], 1); in ddr3_read_leveling_sw() 274 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][D], 2); in ddr3_read_leveling_sw() 1094 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_single_cs_window_mode() [all …]
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/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/ddr/marvell/axp/ |
H A D | ddr3_read_leveling.c | 20 DEBUG_RL_S(s); DEBUG_RL_D(d, l); DEBUG_RL_S("\n") 27 #define DEBUG_RL_D(d, l) \ macro 31 #define DEBUG_RL_D(d, l) macro 138 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_hw() 140 DEBUG_RL_D((u32) dram_info-> in ddr3_read_leveling_hw() 143 DEBUG_RL_D((u32) dram_info-> in ddr3_read_leveling_hw() 270 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_sw() 272 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][P], 1); in ddr3_read_leveling_sw() 274 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][D], 2); in ddr3_read_leveling_sw() 1094 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_single_cs_window_mode() [all …]
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