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Searched refs:DMA1_Channel2_BASE (Results 1 – 24 of 24) sorted by relevance

/dports/devel/openocd/openocd-0.11.0/tcl/chip/st/stm32/
H A Dstm32_regs.tcl60 set DMA1_Channel2_BASE [expr $AHBPERIPH_BASE + 0x001C]
/dports/security/py-pyvex/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/
H A Dstm32l1xx_ll_dma.h68 (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
/dports/devel/py-cle/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/
H A Dstm32l1xx_ll_dma.h68 (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
/dports/security/py-ailment/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/
H A Dstm32l1xx_ll_dma.h68 (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
/dports/security/py-angr/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/
H A Dstm32l1xx_ll_dma.h68 (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32G4xx_HAL_Driver/inc/
H A Dstm32g4xx_ll_dma.h51 (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/CMSIS/CM3_f37x/
H A Dstm32f37x.h895 #define DMA1_Channel2_BASE (AHB1PERIPH_BASE + 0x001C) macro
969 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/CMSIS/CM3_f0xx/
H A Dstm32f0xx.h1057 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C) macro
1130 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/CMSIS/CM3_f37x/
H A Dstm32f37x.h895 #define DMA1_Channel2_BASE (AHB1PERIPH_BASE + 0x001C) macro
969 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/CMSIS/CM3_f10x/
H A Dstm32f10x.h1124 #define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) macro
1206 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/CMSIS/CM3_f10x/
H A Dstm32f10x.h1124 #define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) macro
1206 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
/dports/security/py-pyvex/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/
H A Dstm32l152xe.h737 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CU) macro
824 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
/dports/devel/py-cle/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/
H A Dstm32l152xe.h737 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CU) macro
824 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
/dports/security/py-angr/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/
H A Dstm32l152xe.h737 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CU) macro
824 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
/dports/security/py-ailment/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/
H A Dstm32l152xe.h737 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CU) macro
824 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/CMSIS/CM3_f30x/
H A Dstm32f30x.h1272 #define DMA1_Channel2_BASE (AHB1PERIPH_BASE + 0x0000001C) macro
1381 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/CMSIS/CM3_g4xx/
H A Dstm32g431xx.h1008 #define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL) macro
1146 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
H A Dstm32gbk1cb.h996 #define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL) macro
1132 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
H A Dstm32g441xx.h1040 #define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL) macro
1180 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
H A Dstm32g471xx.h1047 #define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL) macro
1202 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
H A Dstm32g473xx.h1128 #define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL) macro
1303 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
H A Dstm32g483xx.h1160 #define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL) macro
1337 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
H A Dstm32g474xx.h1255 #define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL) macro
1438 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
H A Dstm32g484xx.h1287 #define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL) macro
1472 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)