| /dports/lang/micropython/micropython-1.17/ports/stm32/ |
| H A D | eth.c | 577 if (ETH->DMASR & ETH_DMASR_TBUS) { in eth_tx_buf_send()
578 ETH->DMASR = ETH_DMASR_TBUS; in eth_tx_buf_send()
623 uint32_t sr = ETH->DMASR; in ETH_IRQHandler()
624 ETH->DMASR = ETH_DMASR_NIS; in ETH_IRQHandler()
631 ETH->DMASR = ETH_DMASR_RS; in ETH_IRQHandler()
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| /dports/sysutils/u-boot-utilite/u-boot-2015.07/arch/powerpc/include/asm/ |
| H A D | ppc405.h | 53 #define DMASR (DMA_DCR_BASE + 0x20) /* DMA status reg */ macro
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| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/ |
| H A D | reginfo.c | 297 PRINT_DCR(DMASR); in ppc4xx_reginfo()
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| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/ |
| H A D | reginfo.c | 297 PRINT_DCR(DMASR); in ppc4xx_reginfo()
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| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/ |
| H A D | reginfo.c | 297 PRINT_DCR(DMASR); in ppc4xx_reginfo()
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| /dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/ |
| H A D | reginfo.c | 297 PRINT_DCR(DMASR); in ppc4xx_reginfo()
|
| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/ |
| H A D | reginfo.c | 297 PRINT_DCR(DMASR); in ppc4xx_reginfo()
|
| /dports/emulators/qemu/qemu-6.2.0/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/ |
| H A D | reginfo.c | 297 PRINT_DCR(DMASR); in ppc4xx_reginfo()
|
| /dports/sysutils/u-boot-utilite/u-boot-2015.07/arch/powerpc/cpu/ppc4xx/ |
| H A D | reginfo.c | 284 PRINT_DCR(DMASR); in ppc4xx_reginfo()
|
| /dports/emulators/qemu60/qemu-6.0.0/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/ |
| H A D | reginfo.c | 297 PRINT_DCR(DMASR); in ppc4xx_reginfo()
|
| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/include/ |
| H A D | ppc405.h | 65 #define DMASR (DMA_DCR_BASE+0x20) /* DMA status register */ macro
|
| H A D | ppc440.h | 631 #define DMASR (DMA_DCR_BASE+0x20) /* DMA status register */ macro
|
| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/include/ |
| H A D | ppc405.h | 65 #define DMASR (DMA_DCR_BASE+0x20) /* DMA status register */ macro
|
| H A D | ppc440.h | 631 #define DMASR (DMA_DCR_BASE+0x20) /* DMA status register */ macro
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/include/ |
| H A D | ppc405.h | 65 #define DMASR (DMA_DCR_BASE+0x20) /* DMA status register */ macro
|
| H A D | ppc440.h | 631 #define DMASR (DMA_DCR_BASE+0x20) /* DMA status register */ macro
|
| /dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/include/ |
| H A D | ppc405.h | 65 #define DMASR (DMA_DCR_BASE+0x20) /* DMA status register */ macro
|
| H A D | ppc440.h | 631 #define DMASR (DMA_DCR_BASE+0x20) /* DMA status register */ macro
|
| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot-sam460ex/include/ |
| H A D | ppc405.h | 65 #define DMASR (DMA_DCR_BASE+0x20) /* DMA status register */ macro
|
| H A D | ppc440.h | 631 #define DMASR (DMA_DCR_BASE+0x20) /* DMA status register */ macro
|
| /dports/emulators/qemu/qemu-6.2.0/roms/u-boot-sam460ex/include/ |
| H A D | ppc405.h | 65 #define DMASR (DMA_DCR_BASE+0x20) /* DMA status register */ macro
|
| H A D | ppc440.h | 631 #define DMASR (DMA_DCR_BASE+0x20) /* DMA status register */ macro
|
| /dports/emulators/qemu60/qemu-6.0.0/roms/u-boot-sam460ex/include/ |
| H A D | ppc405.h | 65 #define DMASR (DMA_DCR_BASE+0x20) /* DMA status register */ macro
|
| H A D | ppc440.h | 631 #define DMASR (DMA_DCR_BASE+0x20) /* DMA status register */ macro
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| /dports/devel/asl/asl-current/include/ |
| H A D | stddef60.inc | 77 __defdcr DMASR,0xe0 ; DMA Status Register
|