1 #define DTM_IDCODE 0x01 2 /* 3 * Identifies the release version of this part. 4 */ 5 #define DTM_IDCODE_VERSION_OFFSET 28 6 #define DTM_IDCODE_VERSION_LENGTH 4 7 #define DTM_IDCODE_VERSION (0xf << DTM_IDCODE_VERSION_OFFSET) 8 /* 9 * Identifies the designer's part number of this part. 10 */ 11 #define DTM_IDCODE_PARTNUMBER_OFFSET 12 12 #define DTM_IDCODE_PARTNUMBER_LENGTH 16 13 #define DTM_IDCODE_PARTNUMBER (0xffff << DTM_IDCODE_PARTNUMBER_OFFSET) 14 /* 15 * Identifies the designer/manufacturer of this part. Bits 6:0 must be 16 * bits 6:0 of the designer/manufacturer's Identification Code as 17 * assigned by JEDEC Standard JEP106. Bits 10:7 contain the modulo-16 18 * count of the number of continuation characters (0x7f) in that same 19 * Identification Code. 20 */ 21 #define DTM_IDCODE_MANUFID_OFFSET 1 22 #define DTM_IDCODE_MANUFID_LENGTH 11 23 #define DTM_IDCODE_MANUFID (0x7ff << DTM_IDCODE_MANUFID_OFFSET) 24 #define DTM_IDCODE_1_OFFSET 0 25 #define DTM_IDCODE_1_LENGTH 1 26 #define DTM_IDCODE_1 (0x1 << DTM_IDCODE_1_OFFSET) 27 #define DTM_DTMCS 0x10 28 /* 29 * Writing 1 to this bit does a hard reset of the DTM, 30 * causing the DTM to forget about any outstanding DMI transactions. 31 * In general this should only be used when the Debugger has 32 * reason to expect that the outstanding DMI transaction will never 33 * complete (e.g. a reset condition caused an inflight DMI transaction to 34 * be cancelled). 35 */ 36 #define DTM_DTMCS_DMIHARDRESET_OFFSET 17 37 #define DTM_DTMCS_DMIHARDRESET_LENGTH 1 38 #define DTM_DTMCS_DMIHARDRESET (0x1 << DTM_DTMCS_DMIHARDRESET_OFFSET) 39 /* 40 * Writing 1 to this bit clears the sticky error state 41 * and allows the DTM to retry or complete the previous 42 * transaction. 43 */ 44 #define DTM_DTMCS_DMIRESET_OFFSET 16 45 #define DTM_DTMCS_DMIRESET_LENGTH 1 46 #define DTM_DTMCS_DMIRESET (0x1 << DTM_DTMCS_DMIRESET_OFFSET) 47 /* 48 * This is a hint to the debugger of the minimum number of 49 * cycles a debugger should spend in 50 * Run-Test/Idle after every DMI scan to avoid a `busy' 51 * return code (\Fdmistat of 3). A debugger must still 52 * check \Fdmistat when necessary. 53 * 54 * 0: It is not necessary to enter Run-Test/Idle at all. 55 * 56 * 1: Enter Run-Test/Idle and leave it immediately. 57 * 58 * 2: Enter Run-Test/Idle and stay there for 1 cycle before leaving. 59 * 60 * And so on. 61 */ 62 #define DTM_DTMCS_IDLE_OFFSET 12 63 #define DTM_DTMCS_IDLE_LENGTH 3 64 #define DTM_DTMCS_IDLE (0x7 << DTM_DTMCS_IDLE_OFFSET) 65 /* 66 * 0: No error. 67 * 68 * 1: Reserved. Interpret the same as 2. 69 * 70 * 2: An operation failed (resulted in \Fop of 2). 71 * 72 * 3: An operation was attempted while a DMI access was still in 73 * progress (resulted in \Fop of 3). 74 */ 75 #define DTM_DTMCS_DMISTAT_OFFSET 10 76 #define DTM_DTMCS_DMISTAT_LENGTH 2 77 #define DTM_DTMCS_DMISTAT (0x3 << DTM_DTMCS_DMISTAT_OFFSET) 78 /* 79 * The size of \Faddress in \Rdmi. 80 */ 81 #define DTM_DTMCS_ABITS_OFFSET 4 82 #define DTM_DTMCS_ABITS_LENGTH 6 83 #define DTM_DTMCS_ABITS (0x3f << DTM_DTMCS_ABITS_OFFSET) 84 /* 85 * 0: Version described in spec version 0.11. 86 * 87 * 1: Version described in spec version 0.13 (and later?), which 88 * reduces the DMI data width to 32 bits. 89 * 90 * Other values are reserved for future use. 91 */ 92 #define DTM_DTMCS_VERSION_OFFSET 0 93 #define DTM_DTMCS_VERSION_LENGTH 4 94 #define DTM_DTMCS_VERSION (0xf << DTM_DTMCS_VERSION_OFFSET) 95 #define DTM_DMI 0x11 96 /* 97 * Address used for DMI access. In Update-DR this value is used 98 * to access the DM over the DMI. 99 */ 100 #define DTM_DMI_ADDRESS_OFFSET 34 101 #define DTM_DMI_ADDRESS_LENGTH abits 102 #define DTM_DMI_ADDRESS (((1L<<abits)-1) << DTM_DMI_ADDRESS_OFFSET) 103 /* 104 * The data to send to the DM over the DMI during Update-DR, and 105 * the data returned from the DM as a result of the previous operation. 106 */ 107 #define DTM_DMI_DATA_OFFSET 2 108 #define DTM_DMI_DATA_LENGTH 32 109 #define DTM_DMI_DATA (0xffffffffL << DTM_DMI_DATA_OFFSET) 110 /* 111 * When the debugger writes this field, it has the following meaning: 112 * 113 * 0: Ignore \Fdata and \Faddress. (nop) 114 * 115 * Don't send anything over the DMI during Update-DR. 116 * This operation should never result in a busy or error response. 117 * The address and data reported in the following Capture-DR 118 * are undefined. 119 * 120 * 1: Read from \Faddress. (read) 121 * 122 * 2: Write \Fdata to \Faddress. (write) 123 * 124 * 3: Reserved. 125 * 126 * When the debugger reads this field, it means the following: 127 * 128 * 0: The previous operation completed successfully. 129 * 130 * 1: Reserved. 131 * 132 * 2: A previous operation failed. The data scanned into \Rdmi in 133 * this access will be ignored. This status is sticky and can be 134 * cleared by writing \Fdmireset in \Rdtmcs. 135 * 136 * This indicates that the DM itself responded with an error, e.g. 137 * in the System Bus and Serial Port overflow/underflow cases. 138 * 139 * 3: An operation was attempted while a DMI request is still in 140 * progress. The data scanned into \Rdmi in this access will be 141 * ignored. This status is sticky and can be cleared by writing 142 * \Fdmireset in \Rdtmcs. If a debugger sees this status, it 143 * needs to give the target more TCK edges between Update-DR and 144 * Capture-DR. The simplest way to do that is to add extra transitions 145 * in Run-Test/Idle. 146 * 147 * (The DTM, DM, and/or component may be in different clock domains, 148 * so synchronization may be required. Some relatively fixed number of 149 * TCK ticks may be needed for the request to reach the DM, complete, 150 * and for the response to be synchronized back into the TCK domain.) 151 */ 152 #define DTM_DMI_OP_OFFSET 0 153 #define DTM_DMI_OP_LENGTH 2 154 #define DTM_DMI_OP (0x3L << DTM_DMI_OP_OFFSET) 155 #define CSR_DCSR 0x7b0 156 /* 157 * 0: There is no external debug support. 158 * 159 * 4: External debug support exists as it is described in this document. 160 */ 161 #define CSR_DCSR_XDEBUGVER_OFFSET 28 162 #define CSR_DCSR_XDEBUGVER_LENGTH 4 163 #define CSR_DCSR_XDEBUGVER (0xf << CSR_DCSR_XDEBUGVER_OFFSET) 164 /* 165 * When 1, {\tt ebreak} instructions in Machine Mode enter Debug Mode. 166 */ 167 #define CSR_DCSR_EBREAKM_OFFSET 15 168 #define CSR_DCSR_EBREAKM_LENGTH 1 169 #define CSR_DCSR_EBREAKM (0x1 << CSR_DCSR_EBREAKM_OFFSET) 170 /* 171 * When 1, {\tt ebreak} instructions in Hypervisor Mode enter Debug Mode. 172 */ 173 #define CSR_DCSR_EBREAKH_OFFSET 14 174 #define CSR_DCSR_EBREAKH_LENGTH 1 175 #define CSR_DCSR_EBREAKH (0x1 << CSR_DCSR_EBREAKH_OFFSET) 176 /* 177 * When 1, {\tt ebreak} instructions in Supervisor Mode enter Debug Mode. 178 */ 179 #define CSR_DCSR_EBREAKS_OFFSET 13 180 #define CSR_DCSR_EBREAKS_LENGTH 1 181 #define CSR_DCSR_EBREAKS (0x1 << CSR_DCSR_EBREAKS_OFFSET) 182 /* 183 * When 1, {\tt ebreak} instructions in User/Application Mode enter 184 * Debug Mode. 185 */ 186 #define CSR_DCSR_EBREAKU_OFFSET 12 187 #define CSR_DCSR_EBREAKU_LENGTH 1 188 #define CSR_DCSR_EBREAKU (0x1 << CSR_DCSR_EBREAKU_OFFSET) 189 /* 190 * 0: Increment counters as usual. 191 * 192 * 1: Don't increment any counters while in Debug Mode. This includes 193 * the {\tt cycle} and {\tt instret} CSRs. This is preferred for most 194 * debugging scenarios. 195 * 196 * An implementation may choose not to support writing to this bit. 197 * The debugger must read back the value it writes to check whether 198 * the feature is supported. 199 */ 200 #define CSR_DCSR_STOPCOUNT_OFFSET 10 201 #define CSR_DCSR_STOPCOUNT_LENGTH 1 202 #define CSR_DCSR_STOPCOUNT (0x1 << CSR_DCSR_STOPCOUNT_OFFSET) 203 /* 204 * 0: Increment timers as usual. 205 * 206 * 1: Don't increment any hart-local timers while in Debug Mode. 207 * 208 * An implementation may choose not to support writing to this bit. 209 * The debugger must read back the value it writes to check whether 210 * the feature is supported. 211 */ 212 #define CSR_DCSR_STOPTIME_OFFSET 9 213 #define CSR_DCSR_STOPTIME_LENGTH 1 214 #define CSR_DCSR_STOPTIME (0x1 << CSR_DCSR_STOPTIME_OFFSET) 215 /* 216 * Explains why Debug Mode was entered. 217 * 218 * When there are multiple reasons to enter Debug Mode in a single 219 * cycle, the cause with the highest priority is the one written. 220 * 221 * 1: An {\tt ebreak} instruction was executed. (priority 3) 222 * 223 * 2: The Trigger Module caused a halt. (priority 4) 224 * 225 * 3: \Fhaltreq was set. (priority 2) 226 * 227 * 4: The hart single stepped because \Fstep was set. (priority 1) 228 * 229 * Other values are reserved for future use. 230 */ 231 #define CSR_DCSR_CAUSE_OFFSET 6 232 #define CSR_DCSR_CAUSE_LENGTH 3 233 #define CSR_DCSR_CAUSE (0x7 << CSR_DCSR_CAUSE_OFFSET) 234 /* 235 * When set and not in Debug Mode, the hart will only execute a single 236 * instruction and then enter Debug Mode. 237 * Interrupts are disabled when this bit is set. 238 * If the instruction does not complete due to an exception, 239 * the hart will immediately enter Debug Mode before executing 240 * the trap handler, with appropriate exception registers set. 241 */ 242 #define CSR_DCSR_STEP_OFFSET 2 243 #define CSR_DCSR_STEP_LENGTH 1 244 #define CSR_DCSR_STEP (0x1 << CSR_DCSR_STEP_OFFSET) 245 /* 246 * Contains the privilege level the hart was operating in when Debug 247 * Mode was entered. The encoding is described in Table 248 * \ref{tab:privlevel}. A debugger can change this value to change 249 * the hart's privilege level when exiting Debug Mode. 250 * 251 * Not all privilege levels are supported on all harts. If the 252 * encoding written is not supported or the debugger is not allowed to 253 * change to it, the hart may change to any supported privilege level. 254 */ 255 #define CSR_DCSR_PRV_OFFSET 0 256 #define CSR_DCSR_PRV_LENGTH 2 257 #define CSR_DCSR_PRV (0x3 << CSR_DCSR_PRV_OFFSET) 258 #define CSR_DPC 0x7b1 259 #define CSR_DPC_DPC_OFFSET 0 260 #define CSR_DPC_DPC_LENGTH XLEN 261 #define CSR_DPC_DPC (((1L<<XLEN)-1) << CSR_DPC_DPC_OFFSET) 262 #define CSR_DSCRATCH0 0x7b2 263 #define CSR_DSCRATCH1 0x7b3 264 #define CSR_TSELECT 0x7a0 265 #define CSR_TSELECT_INDEX_OFFSET 0 266 #define CSR_TSELECT_INDEX_LENGTH XLEN 267 #define CSR_TSELECT_INDEX (((1L<<XLEN)-1) << CSR_TSELECT_INDEX_OFFSET) 268 #define CSR_TDATA1 0x7a1 269 /* 270 * 0: There is no trigger at this \Rtselect. 271 * 272 * 1: The trigger is a legacy SiFive address match trigger. These 273 * should not be implemented and aren't further documented here. 274 * 275 * 2: The trigger is an address/data match trigger. The remaining bits 276 * in this register act as described in \Rmcontrol. 277 * 278 * 3: The trigger is an instruction count trigger. The remaining bits 279 * in this register act as described in \Ricount. 280 * 281 * 15: This trigger exists (so enumeration shouldn't terminate), but 282 * is not currently available. 283 * 284 * Other values are reserved for future use. 285 */ 286 #define CSR_TDATA1_TYPE_OFFSET XLEN-4 287 #define CSR_TDATA1_TYPE_LENGTH 4 288 #define CSR_TDATA1_TYPE (0xfL << CSR_TDATA1_TYPE_OFFSET) 289 /* 290 * 0: Both Debug and M Mode can write the {\tt tdata} registers at the 291 * selected \Rtselect. 292 * 293 * 1: Only Debug Mode can write the {\tt tdata} registers at the 294 * selected \Rtselect. Writes from other modes are ignored. 295 * 296 * This bit is only writable from Debug Mode. 297 */ 298 #define CSR_TDATA1_HMODE_OFFSET XLEN-5 299 #define CSR_TDATA1_HMODE_LENGTH 1 300 #define CSR_TDATA1_HMODE (0x1L << CSR_TDATA1_HMODE_OFFSET) 301 /* 302 * Trigger-specific data. 303 */ 304 #define CSR_TDATA1_DATA_OFFSET 0 305 #define CSR_TDATA1_DATA_LENGTH XLEN - 5 306 #define CSR_TDATA1_DATA (((1L<<XLEN - 5)-1) << CSR_TDATA1_DATA_OFFSET) 307 #define CSR_TDATA2 0x7a2 308 #define CSR_TDATA2_DATA_OFFSET 0 309 #define CSR_TDATA2_DATA_LENGTH XLEN 310 #define CSR_TDATA2_DATA (((1L<<XLEN)-1) << CSR_TDATA2_DATA_OFFSET) 311 #define CSR_TDATA3 0x7a3 312 #define CSR_TDATA3_DATA_OFFSET 0 313 #define CSR_TDATA3_DATA_LENGTH XLEN 314 #define CSR_TDATA3_DATA (((1L<<XLEN)-1) << CSR_TDATA3_DATA_OFFSET) 315 #define CSR_MCONTROL 0x7a1 316 #define CSR_MCONTROL_TYPE_OFFSET XLEN-4 317 #define CSR_MCONTROL_TYPE_LENGTH 4 318 #define CSR_MCONTROL_TYPE (0xfL << CSR_MCONTROL_TYPE_OFFSET) 319 #define CSR_MCONTROL_DMODE_OFFSET XLEN-5 320 #define CSR_MCONTROL_DMODE_LENGTH 1 321 #define CSR_MCONTROL_DMODE (0x1L << CSR_MCONTROL_DMODE_OFFSET) 322 /* 323 * Specifies the largest naturally aligned powers-of-two (NAPOT) range 324 * supported by the hardware. The value is the logarithm base 2 of the 325 * number of bytes in that range. A value of 0 indicates that only 326 * exact value matches are supported (one byte range). A value of 63 327 * corresponds to the maximum NAPOT range, which is $2^{63}$ bytes in 328 * size. 329 */ 330 #define CSR_MCONTROL_MASKMAX_OFFSET XLEN-11 331 #define CSR_MCONTROL_MASKMAX_LENGTH 6 332 #define CSR_MCONTROL_MASKMAX (0x3fL << CSR_MCONTROL_MASKMAX_OFFSET) 333 /* 334 * 0: Perform a match on the virtual address. 335 * 336 * 1: Perform a match on the data value loaded/stored, or the 337 * instruction executed. 338 */ 339 #define CSR_MCONTROL_SELECT_OFFSET 19 340 #define CSR_MCONTROL_SELECT_LENGTH 1 341 #define CSR_MCONTROL_SELECT (0x1L << CSR_MCONTROL_SELECT_OFFSET) 342 /* 343 * 0: The action for this trigger will be taken just before the 344 * instruction that triggered it is executed, but after all preceding 345 * instructions are are committed. 346 * 347 * 1: The action for this trigger will be taken after the instruction 348 * that triggered it is executed. It should be taken before the next 349 * instruction is executed, but it is better to implement triggers and 350 * not implement that suggestion than to not implement them at all. 351 * 352 * Most hardware will only implement one timing or the other, possibly 353 * dependent on \Fselect, \Fexecute, \Fload, and \Fstore. This bit 354 * primarily exists for the hardware to communicate to the debugger 355 * what will happen. Hardware may implement the bit fully writable, in 356 * which case the debugger has a little more control. 357 * 358 * Data load triggers with \Ftiming of 0 will result in the same load 359 * happening again when the debugger lets the core run. For data load 360 * triggers, debuggers must first attempt to set the breakpoint with 361 * \Ftiming of 1. 362 * 363 * A chain of triggers that don't all have the same \Ftiming value 364 * will never fire (unless consecutive instructions match the 365 * appropriate triggers). 366 */ 367 #define CSR_MCONTROL_TIMING_OFFSET 18 368 #define CSR_MCONTROL_TIMING_LENGTH 1 369 #define CSR_MCONTROL_TIMING (0x1L << CSR_MCONTROL_TIMING_OFFSET) 370 /* 371 * Determines what happens when this trigger matches. 372 * 373 * 0: Raise a breakpoint exception. (Used when software wants to use 374 * the trigger module without an external debugger attached.) 375 * 376 * 1: Enter Debug Mode. (Only supported when \Fhmode is 1.) 377 * 378 * 2: Start tracing. 379 * 380 * 3: Stop tracing. 381 * 382 * 4: Emit trace data for this match. If it is a data access match, 383 * emit appropriate Load/Store Address/Data. If it is an instruction 384 * execution, emit its PC. 385 * 386 * Other values are reserved for future use. 387 */ 388 #define CSR_MCONTROL_ACTION_OFFSET 12 389 #define CSR_MCONTROL_ACTION_LENGTH 6 390 #define CSR_MCONTROL_ACTION (0x3fL << CSR_MCONTROL_ACTION_OFFSET) 391 /* 392 * 0: When this trigger matches, the configured action is taken. 393 * 394 * 1: While this trigger does not match, it prevents the trigger with 395 * the next index from matching. 396 */ 397 #define CSR_MCONTROL_CHAIN_OFFSET 11 398 #define CSR_MCONTROL_CHAIN_LENGTH 1 399 #define CSR_MCONTROL_CHAIN (0x1L << CSR_MCONTROL_CHAIN_OFFSET) 400 /* 401 * 0: Matches when the value equals \Rtdatatwo. 402 * 403 * 1: Matches when the top M bits of the value match the top M bits of 404 * \Rtdatatwo. M is XLEN-1 minus the index of the least-significant 405 * bit containing 0 in \Rtdatatwo. 406 * 407 * 2: Matches when the value is greater than or equal to \Rtdatatwo. 408 * 409 * 3: Matches when the value is less than \Rtdatatwo. 410 * 411 * 4: Matches when the lower half of the value equals the lower half 412 * of \Rtdatatwo after the lower half of the value is ANDed with the 413 * upper half of \Rtdatatwo. 414 * 415 * 5: Matches when the upper half of the value equals the lower half 416 * of \Rtdatatwo after the upper half of the value is ANDed with the 417 * upper half of \Rtdatatwo. 418 * 419 * Other values are reserved for future use. 420 */ 421 #define CSR_MCONTROL_MATCH_OFFSET 7 422 #define CSR_MCONTROL_MATCH_LENGTH 4 423 #define CSR_MCONTROL_MATCH (0xfL << CSR_MCONTROL_MATCH_OFFSET) 424 /* 425 * When set, enable this trigger in M mode. 426 */ 427 #define CSR_MCONTROL_M_OFFSET 6 428 #define CSR_MCONTROL_M_LENGTH 1 429 #define CSR_MCONTROL_M (0x1L << CSR_MCONTROL_M_OFFSET) 430 /* 431 * When set, enable this trigger in H mode. 432 */ 433 #define CSR_MCONTROL_H_OFFSET 5 434 #define CSR_MCONTROL_H_LENGTH 1 435 #define CSR_MCONTROL_H (0x1L << CSR_MCONTROL_H_OFFSET) 436 /* 437 * When set, enable this trigger in S mode. 438 */ 439 #define CSR_MCONTROL_S_OFFSET 4 440 #define CSR_MCONTROL_S_LENGTH 1 441 #define CSR_MCONTROL_S (0x1L << CSR_MCONTROL_S_OFFSET) 442 /* 443 * When set, enable this trigger in U mode. 444 */ 445 #define CSR_MCONTROL_U_OFFSET 3 446 #define CSR_MCONTROL_U_LENGTH 1 447 #define CSR_MCONTROL_U (0x1L << CSR_MCONTROL_U_OFFSET) 448 /* 449 * When set, the trigger fires on the virtual address or opcode of an 450 * instruction that is executed. 451 */ 452 #define CSR_MCONTROL_EXECUTE_OFFSET 2 453 #define CSR_MCONTROL_EXECUTE_LENGTH 1 454 #define CSR_MCONTROL_EXECUTE (0x1L << CSR_MCONTROL_EXECUTE_OFFSET) 455 /* 456 * When set, the trigger fires on the virtual address or data of a store. 457 */ 458 #define CSR_MCONTROL_STORE_OFFSET 1 459 #define CSR_MCONTROL_STORE_LENGTH 1 460 #define CSR_MCONTROL_STORE (0x1L << CSR_MCONTROL_STORE_OFFSET) 461 /* 462 * When set, the trigger fires on the virtual address or data of a load. 463 */ 464 #define CSR_MCONTROL_LOAD_OFFSET 0 465 #define CSR_MCONTROL_LOAD_LENGTH 1 466 #define CSR_MCONTROL_LOAD (0x1L << CSR_MCONTROL_LOAD_OFFSET) 467 #define CSR_ICOUNT 0x7a1 468 #define CSR_ICOUNT_TYPE_OFFSET XLEN-4 469 #define CSR_ICOUNT_TYPE_LENGTH 4 470 #define CSR_ICOUNT_TYPE (0xfL << CSR_ICOUNT_TYPE_OFFSET) 471 #define CSR_ICOUNT_DMODE_OFFSET XLEN-5 472 #define CSR_ICOUNT_DMODE_LENGTH 1 473 #define CSR_ICOUNT_DMODE (0x1L << CSR_ICOUNT_DMODE_OFFSET) 474 /* 475 * When count is decremented to 0, the trigger fires. Instead of 476 * changing \Fcount from 1 to 0, it is also acceptable for hardware to 477 * clear \Fm, \Fh, \Fs, and \Fu. This allows \Fcount to be hard-wired 478 * to 1 if this register just exists for single step. 479 */ 480 #define CSR_ICOUNT_COUNT_OFFSET 10 481 #define CSR_ICOUNT_COUNT_LENGTH 14 482 #define CSR_ICOUNT_COUNT (0x3fffL << CSR_ICOUNT_COUNT_OFFSET) 483 /* 484 * When set, every instruction completed or exception taken in M mode decrements \Fcount 485 * by 1. 486 */ 487 #define CSR_ICOUNT_M_OFFSET 9 488 #define CSR_ICOUNT_M_LENGTH 1 489 #define CSR_ICOUNT_M (0x1L << CSR_ICOUNT_M_OFFSET) 490 /* 491 * When set, every instruction completed or exception taken in in H mode decrements \Fcount 492 * by 1. 493 */ 494 #define CSR_ICOUNT_H_OFFSET 8 495 #define CSR_ICOUNT_H_LENGTH 1 496 #define CSR_ICOUNT_H (0x1L << CSR_ICOUNT_H_OFFSET) 497 /* 498 * When set, every instruction completed or exception taken in S mode decrements \Fcount 499 * by 1. 500 */ 501 #define CSR_ICOUNT_S_OFFSET 7 502 #define CSR_ICOUNT_S_LENGTH 1 503 #define CSR_ICOUNT_S (0x1L << CSR_ICOUNT_S_OFFSET) 504 /* 505 * When set, every instruction completed or exception taken in U mode decrements \Fcount 506 * by 1. 507 */ 508 #define CSR_ICOUNT_U_OFFSET 6 509 #define CSR_ICOUNT_U_LENGTH 1 510 #define CSR_ICOUNT_U (0x1L << CSR_ICOUNT_U_OFFSET) 511 /* 512 * Determines what happens when this trigger matches. 513 * 514 * 0: Raise a breakpoint exception. (Used when software wants to use the 515 * trigger module without an external debugger attached.) 516 * 517 * 1: Enter Debug Mode. (Only supported when \Fhmode is 1.) 518 * 519 * 2: Start tracing. 520 * 521 * 3: Stop tracing. 522 * 523 * 4: Emit trace data for this match. If it is a data access match, 524 * emit appropriate Load/Store Address/Data. If it is an instruction 525 * execution, emit its PC. 526 * 527 * Other values are reserved for future use. 528 */ 529 #define CSR_ICOUNT_ACTION_OFFSET 0 530 #define CSR_ICOUNT_ACTION_LENGTH 6 531 #define CSR_ICOUNT_ACTION (0x3fL << CSR_ICOUNT_ACTION_OFFSET) 532 #define DMI_DMSTATUS 0x11 533 /* 534 * This field is 1 when all currently selected harts have acknowledged the previous \Fresumereq. 535 */ 536 #define DMI_DMSTATUS_ALLRESUMEACK_OFFSET 17 537 #define DMI_DMSTATUS_ALLRESUMEACK_LENGTH 1 538 #define DMI_DMSTATUS_ALLRESUMEACK (0x1 << DMI_DMSTATUS_ALLRESUMEACK_OFFSET) 539 /* 540 * This field is 1 when any currently selected hart has acknowledged the previous \Fresumereq. 541 */ 542 #define DMI_DMSTATUS_ANYRESUMEACK_OFFSET 16 543 #define DMI_DMSTATUS_ANYRESUMEACK_LENGTH 1 544 #define DMI_DMSTATUS_ANYRESUMEACK (0x1 << DMI_DMSTATUS_ANYRESUMEACK_OFFSET) 545 /* 546 * This field is 1 when all currently selected harts do not exist in this system. 547 */ 548 #define DMI_DMSTATUS_ALLNONEXISTENT_OFFSET 15 549 #define DMI_DMSTATUS_ALLNONEXISTENT_LENGTH 1 550 #define DMI_DMSTATUS_ALLNONEXISTENT (0x1 << DMI_DMSTATUS_ALLNONEXISTENT_OFFSET) 551 /* 552 * This field is 1 when any currently selected hart does not exist in this system. 553 */ 554 #define DMI_DMSTATUS_ANYNONEXISTENT_OFFSET 14 555 #define DMI_DMSTATUS_ANYNONEXISTENT_LENGTH 1 556 #define DMI_DMSTATUS_ANYNONEXISTENT (0x1 << DMI_DMSTATUS_ANYNONEXISTENT_OFFSET) 557 /* 558 * This field is 1 when all currently selected harts are unavailable. 559 */ 560 #define DMI_DMSTATUS_ALLUNAVAIL_OFFSET 13 561 #define DMI_DMSTATUS_ALLUNAVAIL_LENGTH 1 562 #define DMI_DMSTATUS_ALLUNAVAIL (0x1 << DMI_DMSTATUS_ALLUNAVAIL_OFFSET) 563 /* 564 * This field is 1 when any currently selected hart is unavailable. 565 */ 566 #define DMI_DMSTATUS_ANYUNAVAIL_OFFSET 12 567 #define DMI_DMSTATUS_ANYUNAVAIL_LENGTH 1 568 #define DMI_DMSTATUS_ANYUNAVAIL (0x1 << DMI_DMSTATUS_ANYUNAVAIL_OFFSET) 569 /* 570 * This field is 1 when all currently selected harts are running. 571 */ 572 #define DMI_DMSTATUS_ALLRUNNING_OFFSET 11 573 #define DMI_DMSTATUS_ALLRUNNING_LENGTH 1 574 #define DMI_DMSTATUS_ALLRUNNING (0x1 << DMI_DMSTATUS_ALLRUNNING_OFFSET) 575 /* 576 * This field is 1 when any currently selected hart is running. 577 */ 578 #define DMI_DMSTATUS_ANYRUNNING_OFFSET 10 579 #define DMI_DMSTATUS_ANYRUNNING_LENGTH 1 580 #define DMI_DMSTATUS_ANYRUNNING (0x1 << DMI_DMSTATUS_ANYRUNNING_OFFSET) 581 /* 582 * This field is 1 when all currently selected harts are halted. 583 */ 584 #define DMI_DMSTATUS_ALLHALTED_OFFSET 9 585 #define DMI_DMSTATUS_ALLHALTED_LENGTH 1 586 #define DMI_DMSTATUS_ALLHALTED (0x1 << DMI_DMSTATUS_ALLHALTED_OFFSET) 587 /* 588 * This field is 1 when any currently selected hart is halted. 589 */ 590 #define DMI_DMSTATUS_ANYHALTED_OFFSET 8 591 #define DMI_DMSTATUS_ANYHALTED_LENGTH 1 592 #define DMI_DMSTATUS_ANYHALTED (0x1 << DMI_DMSTATUS_ANYHALTED_OFFSET) 593 /* 594 * 0 when authentication is required before using the DM. 1 when the 595 * authentication check has passed. On components that don't implement 596 * authentication, this bit must be preset as 1. 597 */ 598 #define DMI_DMSTATUS_AUTHENTICATED_OFFSET 7 599 #define DMI_DMSTATUS_AUTHENTICATED_LENGTH 1 600 #define DMI_DMSTATUS_AUTHENTICATED (0x1 << DMI_DMSTATUS_AUTHENTICATED_OFFSET) 601 /* 602 * 0: The authentication module is ready to process the next 603 * read/write to \Rauthdata. 604 * 605 * 1: The authentication module is busy. Accessing \Rauthdata results 606 * in unspecified behavior. 607 * 608 * \Fauthbusy only becomes set in immediate response to an access to 609 * \Rauthdata. 610 */ 611 #define DMI_DMSTATUS_AUTHBUSY_OFFSET 6 612 #define DMI_DMSTATUS_AUTHBUSY_LENGTH 1 613 #define DMI_DMSTATUS_AUTHBUSY (0x1 << DMI_DMSTATUS_AUTHBUSY_OFFSET) 614 #define DMI_DMSTATUS_CFGSTRVALID_OFFSET 4 615 #define DMI_DMSTATUS_CFGSTRVALID_LENGTH 1 616 #define DMI_DMSTATUS_CFGSTRVALID (0x1 << DMI_DMSTATUS_CFGSTRVALID_OFFSET) 617 /* 618 * 0: There is no Debug Module present. 619 * 620 * 1: There is a Debug Module and it conforms to version 0.11 of this 621 * specification. 622 * 623 * 2: There is a Debug Module and it conforms to version 0.13 of this 624 * specification. 625 */ 626 #define DMI_DMSTATUS_VERSION_OFFSET 0 627 #define DMI_DMSTATUS_VERSION_LENGTH 4 628 #define DMI_DMSTATUS_VERSION (0xf << DMI_DMSTATUS_VERSION_OFFSET) 629 #define DMI_DMCONTROL 0x10 630 /* 631 * Halt request signal for all currently selected harts. When set to 632 * 1, each selected hart will halt if it is not currently halted. 633 * 634 * Writing 1 or 0 has no effect on a hart which is already halted, but 635 * the bit should be cleared to 0 before the hart is resumed. 636 * Setting both \Fhaltreq and \Fresumereq leads to undefined behavior. 637 * 638 * Writes apply to the new value of \Fhartsel and \Fhasel. 639 */ 640 #define DMI_DMCONTROL_HALTREQ_OFFSET 31 641 #define DMI_DMCONTROL_HALTREQ_LENGTH 1 642 #define DMI_DMCONTROL_HALTREQ (0x1 << DMI_DMCONTROL_HALTREQ_OFFSET) 643 /* 644 * Resume request signal for all currently selected harts. When set to 1, 645 * each selected hart will resume if it is currently halted. 646 * Setting both \Fhaltreq and \Fresumereq leads to undefined behavior. 647 * 648 * Writes apply to the new value of \Fhartsel and \Fhasel. 649 */ 650 #define DMI_DMCONTROL_RESUMEREQ_OFFSET 30 651 #define DMI_DMCONTROL_RESUMEREQ_LENGTH 1 652 #define DMI_DMCONTROL_RESUMEREQ (0x1 << DMI_DMCONTROL_RESUMEREQ_OFFSET) 653 /* 654 * This optional bit controls reset to all the currently selected harts. 655 * To perform a reset the debugger writes 1, and then writes 0 to 656 * deassert the reset signal. 657 * 658 * If this feature is not implemented, the bit always stays 0, so 659 * after writing 1 the debugger can read the register back to see if 660 * the feature is supported. 661 * 662 * Writes apply to the new value of \Fhartsel and \Fhasel. 663 */ 664 #define DMI_DMCONTROL_HARTRESET_OFFSET 29 665 #define DMI_DMCONTROL_HARTRESET_LENGTH 1 666 #define DMI_DMCONTROL_HARTRESET (0x1 << DMI_DMCONTROL_HARTRESET_OFFSET) 667 /* 668 * Selects the definition of currently selected harts. 669 * 670 * 0: There is a single currently selected hart, that selected by \Fhartsel. 671 * 672 * 1: There may be multiple currently selected harts -- that selected by \Fhartsel, 673 * plus those selected by the hart array mask register. 674 * 675 * An implementation which does not implement the hart array mask register 676 * should tie this field to 0. A debugger which wishes to use the hart array 677 * mask register feature should set this bit and read back to see if the functionality 678 * is supported. 679 */ 680 #define DMI_DMCONTROL_HASEL_OFFSET 26 681 #define DMI_DMCONTROL_HASEL_LENGTH 1 682 #define DMI_DMCONTROL_HASEL (0x1 << DMI_DMCONTROL_HASEL_OFFSET) 683 /* 684 * The DM-specific index of the hart to select. This hart is always part of the 685 * currently selected harts. 686 */ 687 #define DMI_DMCONTROL_HARTSEL_OFFSET 16 688 #define DMI_DMCONTROL_HARTSEL_LENGTH 10 689 #define DMI_DMCONTROL_HARTSEL (0x3ff << DMI_DMCONTROL_HARTSEL_OFFSET) 690 /* 691 * This bit controls the reset signal from the DM to the rest of the 692 * system. To perform a system reset the debugger writes 1, 693 * and then writes 0 694 * to deassert the reset. This bit must not reset the Debug Module 695 * registers. What it does reset is platform-specific (it may 696 * reset nothing). 697 */ 698 #define DMI_DMCONTROL_NDMRESET_OFFSET 1 699 #define DMI_DMCONTROL_NDMRESET_LENGTH 1 700 #define DMI_DMCONTROL_NDMRESET (0x1 << DMI_DMCONTROL_NDMRESET_OFFSET) 701 /* 702 * This bit serves as a reset signal for the Debug Module itself. 703 * 704 * 0: The module's state, including authentication mechanism, 705 * takes its reset values (the \Fdmactive bit is the only bit which can 706 * be written to something other than its reset value). 707 * 708 * 1: The module functions normally. 709 * 710 * No other mechanism should exist that may result in resetting the 711 * Debug Module after power up, including the platform's system reset 712 * or Debug Transport reset signals. 713 * 714 * A debugger may pulse this bit low to get the debug module into a 715 * known state. 716 * 717 * Implementations may use this bit to aid debugging, for example by 718 * preventing the Debug Module from being power gated while debugging 719 * is active. 720 */ 721 #define DMI_DMCONTROL_DMACTIVE_OFFSET 0 722 #define DMI_DMCONTROL_DMACTIVE_LENGTH 1 723 #define DMI_DMCONTROL_DMACTIVE (0x1 << DMI_DMCONTROL_DMACTIVE_OFFSET) 724 #define DMI_HARTINFO 0x12 725 /* 726 * Number of {\tt dscratch} registers available for the debugger 727 * to use during program buffer execution, starting from \Rdscratchzero. 728 * The debugger can make no assumptions about the contents of these 729 * registers between commands. 730 */ 731 #define DMI_HARTINFO_NSCRATCH_OFFSET 20 732 #define DMI_HARTINFO_NSCRATCH_LENGTH 4 733 #define DMI_HARTINFO_NSCRATCH (0xf << DMI_HARTINFO_NSCRATCH_OFFSET) 734 /* 735 * 0: The {\tt data} registers are shadowed in the hart by CSR 736 * registers. Each CSR register is XLEN bits in size, and corresponds 737 * to a single argument, per Table~\ref{tab:datareg}. 738 * 739 * 1: The {\tt data} registers are shadowed in the hart's memory map. 740 * Each register takes up 4 bytes in the memory map. 741 */ 742 #define DMI_HARTINFO_DATAACCESS_OFFSET 16 743 #define DMI_HARTINFO_DATAACCESS_LENGTH 1 744 #define DMI_HARTINFO_DATAACCESS (0x1 << DMI_HARTINFO_DATAACCESS_OFFSET) 745 /* 746 * If \Fdataaccess is 0: Number of CSR registers dedicated to 747 * shadowing the {\tt data} registers. 748 * 749 * If \Fdataaccess is 1: Number of 32-bit words in the memory map 750 * dedicated to shadowing the {\tt data} registers. 751 */ 752 #define DMI_HARTINFO_DATASIZE_OFFSET 12 753 #define DMI_HARTINFO_DATASIZE_LENGTH 4 754 #define DMI_HARTINFO_DATASIZE (0xf << DMI_HARTINFO_DATASIZE_OFFSET) 755 /* 756 * If \Fdataaccess is 0: The number of the first CSR dedicated to 757 * shadowing the {\tt data} registers. 758 * 759 * If \Fdataaccess is 1: Signed address of RAM where the {\tt data} 760 * registers are shadowed. 761 */ 762 #define DMI_HARTINFO_DATAADDR_OFFSET 0 763 #define DMI_HARTINFO_DATAADDR_LENGTH 12 764 #define DMI_HARTINFO_DATAADDR (0xfff << DMI_HARTINFO_DATAADDR_OFFSET) 765 #define DMI_HALTSUM 0x13 766 #define DMI_HALTSUM_HALT1023_992_OFFSET 31 767 #define DMI_HALTSUM_HALT1023_992_LENGTH 1 768 #define DMI_HALTSUM_HALT1023_992 (0x1 << DMI_HALTSUM_HALT1023_992_OFFSET) 769 #define DMI_HALTSUM_HALT991_960_OFFSET 30 770 #define DMI_HALTSUM_HALT991_960_LENGTH 1 771 #define DMI_HALTSUM_HALT991_960 (0x1 << DMI_HALTSUM_HALT991_960_OFFSET) 772 #define DMI_HALTSUM_HALT959_928_OFFSET 29 773 #define DMI_HALTSUM_HALT959_928_LENGTH 1 774 #define DMI_HALTSUM_HALT959_928 (0x1 << DMI_HALTSUM_HALT959_928_OFFSET) 775 #define DMI_HALTSUM_HALT927_896_OFFSET 28 776 #define DMI_HALTSUM_HALT927_896_LENGTH 1 777 #define DMI_HALTSUM_HALT927_896 (0x1 << DMI_HALTSUM_HALT927_896_OFFSET) 778 #define DMI_HALTSUM_HALT895_864_OFFSET 27 779 #define DMI_HALTSUM_HALT895_864_LENGTH 1 780 #define DMI_HALTSUM_HALT895_864 (0x1 << DMI_HALTSUM_HALT895_864_OFFSET) 781 #define DMI_HALTSUM_HALT863_832_OFFSET 26 782 #define DMI_HALTSUM_HALT863_832_LENGTH 1 783 #define DMI_HALTSUM_HALT863_832 (0x1 << DMI_HALTSUM_HALT863_832_OFFSET) 784 #define DMI_HALTSUM_HALT831_800_OFFSET 25 785 #define DMI_HALTSUM_HALT831_800_LENGTH 1 786 #define DMI_HALTSUM_HALT831_800 (0x1 << DMI_HALTSUM_HALT831_800_OFFSET) 787 #define DMI_HALTSUM_HALT799_768_OFFSET 24 788 #define DMI_HALTSUM_HALT799_768_LENGTH 1 789 #define DMI_HALTSUM_HALT799_768 (0x1 << DMI_HALTSUM_HALT799_768_OFFSET) 790 #define DMI_HALTSUM_HALT767_736_OFFSET 23 791 #define DMI_HALTSUM_HALT767_736_LENGTH 1 792 #define DMI_HALTSUM_HALT767_736 (0x1 << DMI_HALTSUM_HALT767_736_OFFSET) 793 #define DMI_HALTSUM_HALT735_704_OFFSET 22 794 #define DMI_HALTSUM_HALT735_704_LENGTH 1 795 #define DMI_HALTSUM_HALT735_704 (0x1 << DMI_HALTSUM_HALT735_704_OFFSET) 796 #define DMI_HALTSUM_HALT703_672_OFFSET 21 797 #define DMI_HALTSUM_HALT703_672_LENGTH 1 798 #define DMI_HALTSUM_HALT703_672 (0x1 << DMI_HALTSUM_HALT703_672_OFFSET) 799 #define DMI_HALTSUM_HALT671_640_OFFSET 20 800 #define DMI_HALTSUM_HALT671_640_LENGTH 1 801 #define DMI_HALTSUM_HALT671_640 (0x1 << DMI_HALTSUM_HALT671_640_OFFSET) 802 #define DMI_HALTSUM_HALT639_608_OFFSET 19 803 #define DMI_HALTSUM_HALT639_608_LENGTH 1 804 #define DMI_HALTSUM_HALT639_608 (0x1 << DMI_HALTSUM_HALT639_608_OFFSET) 805 #define DMI_HALTSUM_HALT607_576_OFFSET 18 806 #define DMI_HALTSUM_HALT607_576_LENGTH 1 807 #define DMI_HALTSUM_HALT607_576 (0x1 << DMI_HALTSUM_HALT607_576_OFFSET) 808 #define DMI_HALTSUM_HALT575_544_OFFSET 17 809 #define DMI_HALTSUM_HALT575_544_LENGTH 1 810 #define DMI_HALTSUM_HALT575_544 (0x1 << DMI_HALTSUM_HALT575_544_OFFSET) 811 #define DMI_HALTSUM_HALT543_512_OFFSET 16 812 #define DMI_HALTSUM_HALT543_512_LENGTH 1 813 #define DMI_HALTSUM_HALT543_512 (0x1 << DMI_HALTSUM_HALT543_512_OFFSET) 814 #define DMI_HALTSUM_HALT511_480_OFFSET 15 815 #define DMI_HALTSUM_HALT511_480_LENGTH 1 816 #define DMI_HALTSUM_HALT511_480 (0x1 << DMI_HALTSUM_HALT511_480_OFFSET) 817 #define DMI_HALTSUM_HALT479_448_OFFSET 14 818 #define DMI_HALTSUM_HALT479_448_LENGTH 1 819 #define DMI_HALTSUM_HALT479_448 (0x1 << DMI_HALTSUM_HALT479_448_OFFSET) 820 #define DMI_HALTSUM_HALT447_416_OFFSET 13 821 #define DMI_HALTSUM_HALT447_416_LENGTH 1 822 #define DMI_HALTSUM_HALT447_416 (0x1 << DMI_HALTSUM_HALT447_416_OFFSET) 823 #define DMI_HALTSUM_HALT415_384_OFFSET 12 824 #define DMI_HALTSUM_HALT415_384_LENGTH 1 825 #define DMI_HALTSUM_HALT415_384 (0x1 << DMI_HALTSUM_HALT415_384_OFFSET) 826 #define DMI_HALTSUM_HALT383_352_OFFSET 11 827 #define DMI_HALTSUM_HALT383_352_LENGTH 1 828 #define DMI_HALTSUM_HALT383_352 (0x1 << DMI_HALTSUM_HALT383_352_OFFSET) 829 #define DMI_HALTSUM_HALT351_320_OFFSET 10 830 #define DMI_HALTSUM_HALT351_320_LENGTH 1 831 #define DMI_HALTSUM_HALT351_320 (0x1 << DMI_HALTSUM_HALT351_320_OFFSET) 832 #define DMI_HALTSUM_HALT319_288_OFFSET 9 833 #define DMI_HALTSUM_HALT319_288_LENGTH 1 834 #define DMI_HALTSUM_HALT319_288 (0x1 << DMI_HALTSUM_HALT319_288_OFFSET) 835 #define DMI_HALTSUM_HALT287_256_OFFSET 8 836 #define DMI_HALTSUM_HALT287_256_LENGTH 1 837 #define DMI_HALTSUM_HALT287_256 (0x1 << DMI_HALTSUM_HALT287_256_OFFSET) 838 #define DMI_HALTSUM_HALT255_224_OFFSET 7 839 #define DMI_HALTSUM_HALT255_224_LENGTH 1 840 #define DMI_HALTSUM_HALT255_224 (0x1 << DMI_HALTSUM_HALT255_224_OFFSET) 841 #define DMI_HALTSUM_HALT223_192_OFFSET 6 842 #define DMI_HALTSUM_HALT223_192_LENGTH 1 843 #define DMI_HALTSUM_HALT223_192 (0x1 << DMI_HALTSUM_HALT223_192_OFFSET) 844 #define DMI_HALTSUM_HALT191_160_OFFSET 5 845 #define DMI_HALTSUM_HALT191_160_LENGTH 1 846 #define DMI_HALTSUM_HALT191_160 (0x1 << DMI_HALTSUM_HALT191_160_OFFSET) 847 #define DMI_HALTSUM_HALT159_128_OFFSET 4 848 #define DMI_HALTSUM_HALT159_128_LENGTH 1 849 #define DMI_HALTSUM_HALT159_128 (0x1 << DMI_HALTSUM_HALT159_128_OFFSET) 850 #define DMI_HALTSUM_HALT127_96_OFFSET 3 851 #define DMI_HALTSUM_HALT127_96_LENGTH 1 852 #define DMI_HALTSUM_HALT127_96 (0x1 << DMI_HALTSUM_HALT127_96_OFFSET) 853 #define DMI_HALTSUM_HALT95_64_OFFSET 2 854 #define DMI_HALTSUM_HALT95_64_LENGTH 1 855 #define DMI_HALTSUM_HALT95_64 (0x1 << DMI_HALTSUM_HALT95_64_OFFSET) 856 #define DMI_HALTSUM_HALT63_32_OFFSET 1 857 #define DMI_HALTSUM_HALT63_32_LENGTH 1 858 #define DMI_HALTSUM_HALT63_32 (0x1 << DMI_HALTSUM_HALT63_32_OFFSET) 859 #define DMI_HALTSUM_HALT31_0_OFFSET 0 860 #define DMI_HALTSUM_HALT31_0_LENGTH 1 861 #define DMI_HALTSUM_HALT31_0 (0x1 << DMI_HALTSUM_HALT31_0_OFFSET) 862 #define DMI_HAWINDOWSEL 0x14 863 #define DMI_HAWINDOWSEL_HAWINDOWSEL_OFFSET 0 864 #define DMI_HAWINDOWSEL_HAWINDOWSEL_LENGTH 5 865 #define DMI_HAWINDOWSEL_HAWINDOWSEL (0x1f << DMI_HAWINDOWSEL_HAWINDOWSEL_OFFSET) 866 #define DMI_HAWINDOW 0x15 867 #define DMI_HAWINDOW_MASKDATA_OFFSET 0 868 #define DMI_HAWINDOW_MASKDATA_LENGTH 32 869 #define DMI_HAWINDOW_MASKDATA (0xffffffff << DMI_HAWINDOW_MASKDATA_OFFSET) 870 #define DMI_ABSTRACTCS 0x16 871 /* 872 * Size of the Program Buffer, in 32-bit words. Valid sizes are 0 - 16. 873 * 874 * TODO: Explain what can be done with each size of the buffer, to suggest 875 * why you would want more or less words. 876 */ 877 #define DMI_ABSTRACTCS_PROGSIZE_OFFSET 24 878 #define DMI_ABSTRACTCS_PROGSIZE_LENGTH 5 879 #define DMI_ABSTRACTCS_PROGSIZE (0x1f << DMI_ABSTRACTCS_PROGSIZE_OFFSET) 880 /* 881 * 1: An abstract command is currently being executed. 882 * 883 * This bit is set as soon as \Rcommand is written, and is 884 * not cleared until that command has completed. 885 */ 886 #define DMI_ABSTRACTCS_BUSY_OFFSET 12 887 #define DMI_ABSTRACTCS_BUSY_LENGTH 1 888 #define DMI_ABSTRACTCS_BUSY (0x1 << DMI_ABSTRACTCS_BUSY_OFFSET) 889 /* 890 * Gets set if an abstract command fails. The bits in this field remain set until 891 * they are cleared by writing 1 to them. No abstract command is 892 * started until the value is reset to 0. 893 * 894 * 0 (none): No error. 895 * 896 * 1 (busy): An abstract command was executing while \Rcommand, 897 * \Rabstractcs, \Rabstractauto was written, or when one 898 * of the {\tt data} or {\tt progbuf} registers was read or written. 899 * 900 * 2 (not supported): The requested command is not supported. A 901 * command that is not supported while the hart is running may be 902 * supported when it is halted. 903 * 904 * 3 (exception): An exception occurred while executing the command 905 * (eg. while executing the Program Buffer). 906 * 907 * 4 (halt/resume): An abstract command couldn't execute because the 908 * hart wasn't in the expected state (running/halted). 909 * 910 * 7 (other): The command failed for another reason. 911 */ 912 #define DMI_ABSTRACTCS_CMDERR_OFFSET 8 913 #define DMI_ABSTRACTCS_CMDERR_LENGTH 3 914 #define DMI_ABSTRACTCS_CMDERR (0x7 << DMI_ABSTRACTCS_CMDERR_OFFSET) 915 /* 916 * Number of {\tt data} registers that are implemented as part of the 917 * abstract command interface. Valid sizes are 0 - 12. 918 */ 919 #define DMI_ABSTRACTCS_DATACOUNT_OFFSET 0 920 #define DMI_ABSTRACTCS_DATACOUNT_LENGTH 5 921 #define DMI_ABSTRACTCS_DATACOUNT (0x1f << DMI_ABSTRACTCS_DATACOUNT_OFFSET) 922 #define DMI_COMMAND 0x17 923 /* 924 * The type determines the overall functionality of this 925 * abstract command. 926 */ 927 #define DMI_COMMAND_CMDTYPE_OFFSET 24 928 #define DMI_COMMAND_CMDTYPE_LENGTH 8 929 #define DMI_COMMAND_CMDTYPE (0xff << DMI_COMMAND_CMDTYPE_OFFSET) 930 /* 931 * This field is interpreted in a command-specific manner, 932 * described for each abstract command. 933 */ 934 #define DMI_COMMAND_CONTROL_OFFSET 0 935 #define DMI_COMMAND_CONTROL_LENGTH 24 936 #define DMI_COMMAND_CONTROL (0xffffff << DMI_COMMAND_CONTROL_OFFSET) 937 #define DMI_ABSTRACTAUTO 0x18 938 /* 939 * When a bit in this field is 1, read or write accesses the corresponding {\tt progbuf} word 940 * cause the command in \Rcommand to be executed again. 941 */ 942 #define DMI_ABSTRACTAUTO_AUTOEXECPROGBUF_OFFSET 16 943 #define DMI_ABSTRACTAUTO_AUTOEXECPROGBUF_LENGTH 16 944 #define DMI_ABSTRACTAUTO_AUTOEXECPROGBUF (0xffff << DMI_ABSTRACTAUTO_AUTOEXECPROGBUF_OFFSET) 945 /* 946 * When a bit in this field is 1, read or write accesses the corresponding {\tt data} word 947 * cause the command in \Rcommand to be executed again. 948 */ 949 #define DMI_ABSTRACTAUTO_AUTOEXECDATA_OFFSET 0 950 #define DMI_ABSTRACTAUTO_AUTOEXECDATA_LENGTH 12 951 #define DMI_ABSTRACTAUTO_AUTOEXECDATA (0xfff << DMI_ABSTRACTAUTO_AUTOEXECDATA_OFFSET) 952 #define DMI_CFGSTRADDR0 0x19 953 #define DMI_CFGSTRADDR0_ADDR_OFFSET 0 954 #define DMI_CFGSTRADDR0_ADDR_LENGTH 32 955 #define DMI_CFGSTRADDR0_ADDR (0xffffffff << DMI_CFGSTRADDR0_ADDR_OFFSET) 956 #define DMI_CFGSTRADDR1 0x1a 957 #define DMI_CFGSTRADDR2 0x1b 958 #define DMI_CFGSTRADDR3 0x1c 959 #define DMI_DATA0 0x04 960 #define DMI_DATA0_DATA_OFFSET 0 961 #define DMI_DATA0_DATA_LENGTH 32 962 #define DMI_DATA0_DATA (0xffffffff << DMI_DATA0_DATA_OFFSET) 963 #define DMI_DATA11 0x0f 964 #define DMI_PROGBUF0 0x20 965 #define DMI_PROGBUF0_DATA_OFFSET 0 966 #define DMI_PROGBUF0_DATA_LENGTH 32 967 #define DMI_PROGBUF0_DATA (0xffffffff << DMI_PROGBUF0_DATA_OFFSET) 968 #define DMI_PROGBUF15 0x2f 969 #define DMI_AUTHDATA 0x30 970 #define DMI_AUTHDATA_DATA_OFFSET 0 971 #define DMI_AUTHDATA_DATA_LENGTH 32 972 #define DMI_AUTHDATA_DATA (0xffffffff << DMI_AUTHDATA_DATA_OFFSET) 973 #define DMI_SERCS 0x34 974 /* 975 * Number of supported serial ports. 976 */ 977 #define DMI_SERCS_SERIALCOUNT_OFFSET 28 978 #define DMI_SERCS_SERIALCOUNT_LENGTH 4 979 #define DMI_SERCS_SERIALCOUNT (0xf << DMI_SERCS_SERIALCOUNT_OFFSET) 980 /* 981 * Select which serial port is accessed by \Rserrx and \Rsertx. 982 */ 983 #define DMI_SERCS_SERIAL_OFFSET 24 984 #define DMI_SERCS_SERIAL_LENGTH 3 985 #define DMI_SERCS_SERIAL (0x7 << DMI_SERCS_SERIAL_OFFSET) 986 #define DMI_SERCS_ERROR7_OFFSET 23 987 #define DMI_SERCS_ERROR7_LENGTH 1 988 #define DMI_SERCS_ERROR7 (0x1 << DMI_SERCS_ERROR7_OFFSET) 989 #define DMI_SERCS_VALID7_OFFSET 22 990 #define DMI_SERCS_VALID7_LENGTH 1 991 #define DMI_SERCS_VALID7 (0x1 << DMI_SERCS_VALID7_OFFSET) 992 #define DMI_SERCS_FULL7_OFFSET 21 993 #define DMI_SERCS_FULL7_LENGTH 1 994 #define DMI_SERCS_FULL7 (0x1 << DMI_SERCS_FULL7_OFFSET) 995 #define DMI_SERCS_ERROR6_OFFSET 20 996 #define DMI_SERCS_ERROR6_LENGTH 1 997 #define DMI_SERCS_ERROR6 (0x1 << DMI_SERCS_ERROR6_OFFSET) 998 #define DMI_SERCS_VALID6_OFFSET 19 999 #define DMI_SERCS_VALID6_LENGTH 1 1000 #define DMI_SERCS_VALID6 (0x1 << DMI_SERCS_VALID6_OFFSET) 1001 #define DMI_SERCS_FULL6_OFFSET 18 1002 #define DMI_SERCS_FULL6_LENGTH 1 1003 #define DMI_SERCS_FULL6 (0x1 << DMI_SERCS_FULL6_OFFSET) 1004 #define DMI_SERCS_ERROR5_OFFSET 17 1005 #define DMI_SERCS_ERROR5_LENGTH 1 1006 #define DMI_SERCS_ERROR5 (0x1 << DMI_SERCS_ERROR5_OFFSET) 1007 #define DMI_SERCS_VALID5_OFFSET 16 1008 #define DMI_SERCS_VALID5_LENGTH 1 1009 #define DMI_SERCS_VALID5 (0x1 << DMI_SERCS_VALID5_OFFSET) 1010 #define DMI_SERCS_FULL5_OFFSET 15 1011 #define DMI_SERCS_FULL5_LENGTH 1 1012 #define DMI_SERCS_FULL5 (0x1 << DMI_SERCS_FULL5_OFFSET) 1013 #define DMI_SERCS_ERROR4_OFFSET 14 1014 #define DMI_SERCS_ERROR4_LENGTH 1 1015 #define DMI_SERCS_ERROR4 (0x1 << DMI_SERCS_ERROR4_OFFSET) 1016 #define DMI_SERCS_VALID4_OFFSET 13 1017 #define DMI_SERCS_VALID4_LENGTH 1 1018 #define DMI_SERCS_VALID4 (0x1 << DMI_SERCS_VALID4_OFFSET) 1019 #define DMI_SERCS_FULL4_OFFSET 12 1020 #define DMI_SERCS_FULL4_LENGTH 1 1021 #define DMI_SERCS_FULL4 (0x1 << DMI_SERCS_FULL4_OFFSET) 1022 #define DMI_SERCS_ERROR3_OFFSET 11 1023 #define DMI_SERCS_ERROR3_LENGTH 1 1024 #define DMI_SERCS_ERROR3 (0x1 << DMI_SERCS_ERROR3_OFFSET) 1025 #define DMI_SERCS_VALID3_OFFSET 10 1026 #define DMI_SERCS_VALID3_LENGTH 1 1027 #define DMI_SERCS_VALID3 (0x1 << DMI_SERCS_VALID3_OFFSET) 1028 #define DMI_SERCS_FULL3_OFFSET 9 1029 #define DMI_SERCS_FULL3_LENGTH 1 1030 #define DMI_SERCS_FULL3 (0x1 << DMI_SERCS_FULL3_OFFSET) 1031 #define DMI_SERCS_ERROR2_OFFSET 8 1032 #define DMI_SERCS_ERROR2_LENGTH 1 1033 #define DMI_SERCS_ERROR2 (0x1 << DMI_SERCS_ERROR2_OFFSET) 1034 #define DMI_SERCS_VALID2_OFFSET 7 1035 #define DMI_SERCS_VALID2_LENGTH 1 1036 #define DMI_SERCS_VALID2 (0x1 << DMI_SERCS_VALID2_OFFSET) 1037 #define DMI_SERCS_FULL2_OFFSET 6 1038 #define DMI_SERCS_FULL2_LENGTH 1 1039 #define DMI_SERCS_FULL2 (0x1 << DMI_SERCS_FULL2_OFFSET) 1040 #define DMI_SERCS_ERROR1_OFFSET 5 1041 #define DMI_SERCS_ERROR1_LENGTH 1 1042 #define DMI_SERCS_ERROR1 (0x1 << DMI_SERCS_ERROR1_OFFSET) 1043 #define DMI_SERCS_VALID1_OFFSET 4 1044 #define DMI_SERCS_VALID1_LENGTH 1 1045 #define DMI_SERCS_VALID1 (0x1 << DMI_SERCS_VALID1_OFFSET) 1046 #define DMI_SERCS_FULL1_OFFSET 3 1047 #define DMI_SERCS_FULL1_LENGTH 1 1048 #define DMI_SERCS_FULL1 (0x1 << DMI_SERCS_FULL1_OFFSET) 1049 /* 1050 * 1 when the debugger-to-core queue for serial port 0 has 1051 * over or underflowed. This bit will remain set until it is reset by 1052 * writing 1 to this bit. 1053 */ 1054 #define DMI_SERCS_ERROR0_OFFSET 2 1055 #define DMI_SERCS_ERROR0_LENGTH 1 1056 #define DMI_SERCS_ERROR0 (0x1 << DMI_SERCS_ERROR0_OFFSET) 1057 /* 1058 * 1 when the core-to-debugger queue for serial port 0 is not empty. 1059 */ 1060 #define DMI_SERCS_VALID0_OFFSET 1 1061 #define DMI_SERCS_VALID0_LENGTH 1 1062 #define DMI_SERCS_VALID0 (0x1 << DMI_SERCS_VALID0_OFFSET) 1063 /* 1064 * 1 when the debugger-to-core queue for serial port 0 is full. 1065 */ 1066 #define DMI_SERCS_FULL0_OFFSET 0 1067 #define DMI_SERCS_FULL0_LENGTH 1 1068 #define DMI_SERCS_FULL0 (0x1 << DMI_SERCS_FULL0_OFFSET) 1069 #define DMI_SERTX 0x35 1070 #define DMI_SERTX_DATA_OFFSET 0 1071 #define DMI_SERTX_DATA_LENGTH 32 1072 #define DMI_SERTX_DATA (0xffffffff << DMI_SERTX_DATA_OFFSET) 1073 #define DMI_SERRX 0x36 1074 #define DMI_SERRX_DATA_OFFSET 0 1075 #define DMI_SERRX_DATA_LENGTH 32 1076 #define DMI_SERRX_DATA (0xffffffff << DMI_SERRX_DATA_OFFSET) 1077 #define DMI_SBCS 0x38 1078 /* 1079 * When a 1 is written here, triggers a read at the address in {\tt 1080 * sbaddress} using the access size set by \Fsbaccess. 1081 */ 1082 #define DMI_SBCS_SBSINGLEREAD_OFFSET 20 1083 #define DMI_SBCS_SBSINGLEREAD_LENGTH 1 1084 #define DMI_SBCS_SBSINGLEREAD (0x1 << DMI_SBCS_SBSINGLEREAD_OFFSET) 1085 /* 1086 * Select the access size to use for system bus accesses triggered by 1087 * writes to the {\tt sbaddress} registers or \Rsbdatazero. 1088 * 1089 * 0: 8-bit 1090 * 1091 * 1: 16-bit 1092 * 1093 * 2: 32-bit 1094 * 1095 * 3: 64-bit 1096 * 1097 * 4: 128-bit 1098 * 1099 * If an unsupported system bus access size is written here, 1100 * the DM may not perform the access, or may perform the access 1101 * with any access size. 1102 */ 1103 #define DMI_SBCS_SBACCESS_OFFSET 17 1104 #define DMI_SBCS_SBACCESS_LENGTH 3 1105 #define DMI_SBCS_SBACCESS (0x7 << DMI_SBCS_SBACCESS_OFFSET) 1106 /* 1107 * When 1, the internal address value (used by the system bus master) 1108 * is incremented by the access size (in bytes) selected in \Fsbaccess 1109 * after every system bus access. 1110 */ 1111 #define DMI_SBCS_SBAUTOINCREMENT_OFFSET 16 1112 #define DMI_SBCS_SBAUTOINCREMENT_LENGTH 1 1113 #define DMI_SBCS_SBAUTOINCREMENT (0x1 << DMI_SBCS_SBAUTOINCREMENT_OFFSET) 1114 /* 1115 * When 1, every read from \Rsbdatazero automatically triggers a system 1116 * bus read at the new address. 1117 */ 1118 #define DMI_SBCS_SBAUTOREAD_OFFSET 15 1119 #define DMI_SBCS_SBAUTOREAD_LENGTH 1 1120 #define DMI_SBCS_SBAUTOREAD (0x1 << DMI_SBCS_SBAUTOREAD_OFFSET) 1121 /* 1122 * When the debug module's system bus 1123 * master causes a bus error, this field gets set. The bits in this 1124 * field remain set until they are cleared by writing 1 to them. 1125 * While this field is non-zero, no more system bus accesses can be 1126 * initiated by the debug module. 1127 * 1128 * 0: There was no bus error. 1129 * 1130 * 1: There was a timeout. 1131 * 1132 * 2: A bad address was accessed. 1133 * 1134 * 3: There was some other error (eg. alignment). 1135 * 1136 * 4: The system bus master was busy when one of the 1137 * {\tt sbaddress} or {\tt sbdata} registers was written, 1138 * or the {\tt sbdata} register was read when it had 1139 * stale data. 1140 */ 1141 #define DMI_SBCS_SBERROR_OFFSET 12 1142 #define DMI_SBCS_SBERROR_LENGTH 3 1143 #define DMI_SBCS_SBERROR (0x7 << DMI_SBCS_SBERROR_OFFSET) 1144 /* 1145 * Width of system bus addresses in bits. (0 indicates there is no bus 1146 * access support.) 1147 */ 1148 #define DMI_SBCS_SBASIZE_OFFSET 5 1149 #define DMI_SBCS_SBASIZE_LENGTH 7 1150 #define DMI_SBCS_SBASIZE (0x7f << DMI_SBCS_SBASIZE_OFFSET) 1151 /* 1152 * 1 when 128-bit system bus accesses are supported. 1153 */ 1154 #define DMI_SBCS_SBACCESS128_OFFSET 4 1155 #define DMI_SBCS_SBACCESS128_LENGTH 1 1156 #define DMI_SBCS_SBACCESS128 (0x1 << DMI_SBCS_SBACCESS128_OFFSET) 1157 /* 1158 * 1 when 64-bit system bus accesses are supported. 1159 */ 1160 #define DMI_SBCS_SBACCESS64_OFFSET 3 1161 #define DMI_SBCS_SBACCESS64_LENGTH 1 1162 #define DMI_SBCS_SBACCESS64 (0x1 << DMI_SBCS_SBACCESS64_OFFSET) 1163 /* 1164 * 1 when 32-bit system bus accesses are supported. 1165 */ 1166 #define DMI_SBCS_SBACCESS32_OFFSET 2 1167 #define DMI_SBCS_SBACCESS32_LENGTH 1 1168 #define DMI_SBCS_SBACCESS32 (0x1 << DMI_SBCS_SBACCESS32_OFFSET) 1169 /* 1170 * 1 when 16-bit system bus accesses are supported. 1171 */ 1172 #define DMI_SBCS_SBACCESS16_OFFSET 1 1173 #define DMI_SBCS_SBACCESS16_LENGTH 1 1174 #define DMI_SBCS_SBACCESS16 (0x1 << DMI_SBCS_SBACCESS16_OFFSET) 1175 /* 1176 * 1 when 8-bit system bus accesses are supported. 1177 */ 1178 #define DMI_SBCS_SBACCESS8_OFFSET 0 1179 #define DMI_SBCS_SBACCESS8_LENGTH 1 1180 #define DMI_SBCS_SBACCESS8 (0x1 << DMI_SBCS_SBACCESS8_OFFSET) 1181 #define DMI_SBADDRESS0 0x39 1182 /* 1183 * Accesses bits 31:0 of the internal address. 1184 */ 1185 #define DMI_SBADDRESS0_ADDRESS_OFFSET 0 1186 #define DMI_SBADDRESS0_ADDRESS_LENGTH 32 1187 #define DMI_SBADDRESS0_ADDRESS (0xffffffff << DMI_SBADDRESS0_ADDRESS_OFFSET) 1188 #define DMI_SBADDRESS1 0x3a 1189 /* 1190 * Accesses bits 63:32 of the internal address (if the system address 1191 * bus is that wide). 1192 */ 1193 #define DMI_SBADDRESS1_ADDRESS_OFFSET 0 1194 #define DMI_SBADDRESS1_ADDRESS_LENGTH 32 1195 #define DMI_SBADDRESS1_ADDRESS (0xffffffff << DMI_SBADDRESS1_ADDRESS_OFFSET) 1196 #define DMI_SBADDRESS2 0x3b 1197 /* 1198 * Accesses bits 95:64 of the internal address (if the system address 1199 * bus is that wide). 1200 */ 1201 #define DMI_SBADDRESS2_ADDRESS_OFFSET 0 1202 #define DMI_SBADDRESS2_ADDRESS_LENGTH 32 1203 #define DMI_SBADDRESS2_ADDRESS (0xffffffff << DMI_SBADDRESS2_ADDRESS_OFFSET) 1204 #define DMI_SBDATA0 0x3c 1205 /* 1206 * Accesses bits 31:0 of the internal data. 1207 */ 1208 #define DMI_SBDATA0_DATA_OFFSET 0 1209 #define DMI_SBDATA0_DATA_LENGTH 32 1210 #define DMI_SBDATA0_DATA (0xffffffff << DMI_SBDATA0_DATA_OFFSET) 1211 #define DMI_SBDATA1 0x3d 1212 /* 1213 * Accesses bits 63:32 of the internal data (if the system bus is 1214 * that wide). 1215 */ 1216 #define DMI_SBDATA1_DATA_OFFSET 0 1217 #define DMI_SBDATA1_DATA_LENGTH 32 1218 #define DMI_SBDATA1_DATA (0xffffffff << DMI_SBDATA1_DATA_OFFSET) 1219 #define DMI_SBDATA2 0x3e 1220 /* 1221 * Accesses bits 95:64 of the internal data (if the system bus is 1222 * that wide). 1223 */ 1224 #define DMI_SBDATA2_DATA_OFFSET 0 1225 #define DMI_SBDATA2_DATA_LENGTH 32 1226 #define DMI_SBDATA2_DATA (0xffffffff << DMI_SBDATA2_DATA_OFFSET) 1227 #define DMI_SBDATA3 0x3f 1228 /* 1229 * Accesses bits 127:96 of the internal data (if the system bus is 1230 * that wide). 1231 */ 1232 #define DMI_SBDATA3_DATA_OFFSET 0 1233 #define DMI_SBDATA3_DATA_LENGTH 32 1234 #define DMI_SBDATA3_DATA (0xffffffff << DMI_SBDATA3_DATA_OFFSET) 1235 #define TRACE 0x728 1236 /* 1237 * 1 if the trace buffer has wrapped since the last time \Fdiscard was 1238 * written. 0 otherwise. 1239 */ 1240 #define TRACE_WRAPPED_OFFSET 24 1241 #define TRACE_WRAPPED_LENGTH 1 1242 #define TRACE_WRAPPED (0x1 << TRACE_WRAPPED_OFFSET) 1243 /* 1244 * Emit Timestamp trace sequences. 1245 */ 1246 #define TRACE_EMITTIMESTAMP_OFFSET 23 1247 #define TRACE_EMITTIMESTAMP_LENGTH 1 1248 #define TRACE_EMITTIMESTAMP (0x1 << TRACE_EMITTIMESTAMP_OFFSET) 1249 /* 1250 * Emit Store Data trace sequences. 1251 */ 1252 #define TRACE_EMITSTOREDATA_OFFSET 22 1253 #define TRACE_EMITSTOREDATA_LENGTH 1 1254 #define TRACE_EMITSTOREDATA (0x1 << TRACE_EMITSTOREDATA_OFFSET) 1255 /* 1256 * Emit Load Data trace sequences. 1257 */ 1258 #define TRACE_EMITLOADDATA_OFFSET 21 1259 #define TRACE_EMITLOADDATA_LENGTH 1 1260 #define TRACE_EMITLOADDATA (0x1 << TRACE_EMITLOADDATA_OFFSET) 1261 /* 1262 * Emit Store Address trace sequences. 1263 */ 1264 #define TRACE_EMITSTOREADDR_OFFSET 20 1265 #define TRACE_EMITSTOREADDR_LENGTH 1 1266 #define TRACE_EMITSTOREADDR (0x1 << TRACE_EMITSTOREADDR_OFFSET) 1267 /* 1268 * Emit Load Address trace sequences. 1269 */ 1270 #define TRACE_EMITLOADADDR_OFFSET 19 1271 #define TRACE_EMITLOADADDR_LENGTH 1 1272 #define TRACE_EMITLOADADDR (0x1 << TRACE_EMITLOADADDR_OFFSET) 1273 /* 1274 * Emit Privilege Level trace sequences. 1275 */ 1276 #define TRACE_EMITPRIV_OFFSET 18 1277 #define TRACE_EMITPRIV_LENGTH 1 1278 #define TRACE_EMITPRIV (0x1 << TRACE_EMITPRIV_OFFSET) 1279 /* 1280 * Emit Branch Taken and Branch Not Taken trace sequences. 1281 */ 1282 #define TRACE_EMITBRANCH_OFFSET 17 1283 #define TRACE_EMITBRANCH_LENGTH 1 1284 #define TRACE_EMITBRANCH (0x1 << TRACE_EMITBRANCH_OFFSET) 1285 /* 1286 * Emit PC trace sequences. 1287 */ 1288 #define TRACE_EMITPC_OFFSET 16 1289 #define TRACE_EMITPC_LENGTH 1 1290 #define TRACE_EMITPC (0x1 << TRACE_EMITPC_OFFSET) 1291 /* 1292 * Determine what happens when the trace buffer is full. 0 means wrap 1293 * and overwrite. 1 means turn off trace until \Fdiscard is written as 1. 1294 * 2 means cause a trace full exception. 3 is reserved for future use. 1295 */ 1296 #define TRACE_FULLACTION_OFFSET 8 1297 #define TRACE_FULLACTION_LENGTH 2 1298 #define TRACE_FULLACTION (0x3 << TRACE_FULLACTION_OFFSET) 1299 /* 1300 * 0: Trace to a dedicated on-core RAM (which is not further defined in 1301 * this spec). 1302 * 1303 * 1: Trace to RAM on the system bus. 1304 * 1305 * 2: Send trace data to a dedicated off-chip interface (which is not 1306 * defined in this spec). This does not affect execution speed. 1307 * 1308 * 3: Reserved for future use. 1309 * 1310 * Options 0 and 1 slow down execution (eg. because of system bus 1311 * contention). 1312 */ 1313 #define TRACE_DESTINATION_OFFSET 4 1314 #define TRACE_DESTINATION_LENGTH 2 1315 #define TRACE_DESTINATION (0x3 << TRACE_DESTINATION_OFFSET) 1316 /* 1317 * When 1, the trace logic may stall processor execution to ensure it 1318 * can emit all the trace sequences required. When 0 individual trace 1319 * sequences may be dropped. 1320 */ 1321 #define TRACE_STALL_OFFSET 2 1322 #define TRACE_STALL_LENGTH 1 1323 #define TRACE_STALL (0x1 << TRACE_STALL_OFFSET) 1324 /* 1325 * Writing 1 to this bit tells the trace logic that any trace 1326 * collected is no longer required. When tracing to RAM, it resets the 1327 * trace write pointer to the start of the memory, as well as 1328 * \Fwrapped. 1329 */ 1330 #define TRACE_DISCARD_OFFSET 1 1331 #define TRACE_DISCARD_LENGTH 1 1332 #define TRACE_DISCARD (0x1 << TRACE_DISCARD_OFFSET) 1333 #define TRACE_SUPPORTED_OFFSET 0 1334 #define TRACE_SUPPORTED_LENGTH 1 1335 #define TRACE_SUPPORTED (0x1 << TRACE_SUPPORTED_OFFSET) 1336 #define TBUFSTART 0x729 1337 #define TBUFEND 0x72a 1338 #define TBUFWRITE 0x72b 1339 #define SHORTNAME 0x123 1340 /* 1341 * Description of what this field is used for. 1342 */ 1343 #define SHORTNAME_FIELD_OFFSET 0 1344 #define SHORTNAME_FIELD_LENGTH 8 1345 #define SHORTNAME_FIELD (0xff << SHORTNAME_FIELD_OFFSET) 1346 #define AC_ACCESS_REGISTER None 1347 /* 1348 * This is 0 to indicate Access Register Command. 1349 */ 1350 #define AC_ACCESS_REGISTER_CMDTYPE_OFFSET 24 1351 #define AC_ACCESS_REGISTER_CMDTYPE_LENGTH 8 1352 #define AC_ACCESS_REGISTER_CMDTYPE (0xff << AC_ACCESS_REGISTER_CMDTYPE_OFFSET) 1353 /* 1354 * 2: Access the lowest 32 bits of the register. 1355 * 1356 * 3: Access the lowest 64 bits of the register. 1357 * 1358 * 4: Access the lowest 128 bits of the register. 1359 * 1360 * If \Fsize specifies a size larger than the register's actual size, 1361 * then the access must fail. If a register is accessible, then reads of \Fsize 1362 * less than or equal to the register's actual size must be supported. 1363 */ 1364 #define AC_ACCESS_REGISTER_SIZE_OFFSET 20 1365 #define AC_ACCESS_REGISTER_SIZE_LENGTH 3 1366 #define AC_ACCESS_REGISTER_SIZE (0x7 << AC_ACCESS_REGISTER_SIZE_OFFSET) 1367 /* 1368 * When 1, execute the program in the Program Buffer exactly once 1369 * after performing the transfer, if any. 1370 */ 1371 #define AC_ACCESS_REGISTER_POSTEXEC_OFFSET 18 1372 #define AC_ACCESS_REGISTER_POSTEXEC_LENGTH 1 1373 #define AC_ACCESS_REGISTER_POSTEXEC (0x1 << AC_ACCESS_REGISTER_POSTEXEC_OFFSET) 1374 /* 1375 * 0: Don't do the operation specified by \Fwrite. 1376 * 1377 * 1: Do the operation specified by \Fwrite. 1378 */ 1379 #define AC_ACCESS_REGISTER_TRANSFER_OFFSET 17 1380 #define AC_ACCESS_REGISTER_TRANSFER_LENGTH 1 1381 #define AC_ACCESS_REGISTER_TRANSFER (0x1 << AC_ACCESS_REGISTER_TRANSFER_OFFSET) 1382 /* 1383 * When \Ftransfer is set: 1384 * 0: Copy data from the specified register into {\tt arg0} portion 1385 * of {\tt data}. 1386 * 1387 * 1: Copy data from {\tt arg0} portion of {\tt data} into the 1388 * specified register. 1389 */ 1390 #define AC_ACCESS_REGISTER_WRITE_OFFSET 16 1391 #define AC_ACCESS_REGISTER_WRITE_LENGTH 1 1392 #define AC_ACCESS_REGISTER_WRITE (0x1 << AC_ACCESS_REGISTER_WRITE_OFFSET) 1393 /* 1394 * Number of the register to access, as described in 1395 * Table~\ref{tab:regno}. 1396 * \Rdpc may be used as an alias for PC if this command is 1397 * supported on a non-halted hart. 1398 */ 1399 #define AC_ACCESS_REGISTER_REGNO_OFFSET 0 1400 #define AC_ACCESS_REGISTER_REGNO_LENGTH 16 1401 #define AC_ACCESS_REGISTER_REGNO (0xffff << AC_ACCESS_REGISTER_REGNO_OFFSET) 1402 #define AC_QUICK_ACCESS None 1403 /* 1404 * This is 1 to indicate Quick Access command. 1405 */ 1406 #define AC_QUICK_ACCESS_CMDTYPE_OFFSET 24 1407 #define AC_QUICK_ACCESS_CMDTYPE_LENGTH 8 1408 #define AC_QUICK_ACCESS_CMDTYPE (0xff << AC_QUICK_ACCESS_CMDTYPE_OFFSET) 1409 #define VIRT_PRIV virtual 1410 /* 1411 * Contains the privilege level the hart was operating in when Debug 1412 * Mode was entered. The encoding is described in Table 1413 * \ref{tab:privlevel}. A user can write this value to change the 1414 * hart's privilege level when exiting Debug Mode. 1415 */ 1416 #define VIRT_PRIV_PRV_OFFSET 0 1417 #define VIRT_PRIV_PRV_LENGTH 2 1418 #define VIRT_PRIV_PRV (0x3 << VIRT_PRIV_PRV_OFFSET) 1419