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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/Mips/llvm-ir/
H A Dret.ll15 …rch=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
16 …rch=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
17 …rch=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
18 …rch=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
19 …rch=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
26 …6 -asm-show-inst -disable-mips-delay-filler < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,R6C
166 ; DMTC1-DAG: mtc1 $zero, $f0
198 ; DMTC1-DAG: dmtc1 $zero, $f0
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/Mips/llvm-ir/
H A Dret.ll15 …rch=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
16 …rch=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
17 …rch=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
18 …rch=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
19 …rch=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
26 …6 -asm-show-inst -disable-mips-delay-filler < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,R6C
166 ; DMTC1-DAG: mtc1 $zero, $f0
198 ; DMTC1-DAG: dmtc1 $zero, $f0
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/Mips/llvm-ir/
H A Dret.ll15 …rch=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
16 …rch=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
17 …rch=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
18 …rch=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
19 …rch=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
26 …6 -asm-show-inst -disable-mips-delay-filler < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,R6C
166 ; DMTC1-DAG: mtc1 $zero, $f0
198 ; DMTC1-DAG: dmtc1 $zero, $f0
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/Mips/llvm-ir/
H A Dret.ll15 …rch=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
16 …rch=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
17 …rch=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
18 …rch=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
19 …rch=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
26 …6 -asm-show-inst -disable-mips-delay-filler < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,R6C
166 ; DMTC1-DAG: mtc1 $zero, $f0
198 ; DMTC1-DAG: dmtc1 $zero, $f0
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/Mips/llvm-ir/
H A Dret.ll15 …rch=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
16 …rch=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
17 …rch=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
18 …rch=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
19 …rch=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
26 …6 -asm-show-inst -disable-mips-delay-filler < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,R6C
166 ; DMTC1-DAG: mtc1 $zero, $f0
198 ; DMTC1-DAG: dmtc1 $zero, $f0
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/Mips/llvm-ir/
H A Dret.ll15 …rch=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
16 …rch=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
17 …rch=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
18 …rch=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
19 …rch=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
26 …6 -asm-show-inst -disable-mips-delay-filler < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,R6C
166 ; DMTC1-DAG: mtc1 $zero, $f0
198 ; DMTC1-DAG: dmtc1 $zero, $f0
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/Mips/llvm-ir/
H A Dret.ll15 …rch=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
16 …rch=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
17 …rch=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
18 …rch=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
19 …rch=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
26 …6 -asm-show-inst -disable-mips-delay-filler < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,R6C
166 ; DMTC1-DAG: mtc1 $zero, $f0
198 ; DMTC1-DAG: dmtc1 $zero, $f0
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/Mips/llvm-ir/
H A Dret.ll15 …rch=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
16 …rch=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
17 …rch=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
18 …rch=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
19 …rch=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
26 …6 -asm-show-inst -disable-mips-delay-filler < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,R6C
/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/Mips/llvm-ir/
H A Dret.ll15 …rch=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
16 …rch=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
17 …rch=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
18 …rch=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
19 …rch=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
26 …6 -asm-show-inst -disable-mips-delay-filler < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,R6C
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/Mips/llvm-ir/
H A Dret.ll15 …rch=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
16 …rch=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
17 …rch=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
18 …rch=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
19 …rch=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
26 …6 -asm-show-inst -disable-mips-delay-filler < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,R6C
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/Mips/llvm-ir/
H A Dret.ll15 …rch=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
16 …rch=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
17 …rch=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
18 …rch=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
19 …rch=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
26 …6 -asm-show-inst -disable-mips-delay-filler < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,R6C
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/Mips/llvm-ir/
H A Dret.ll15 …rch=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
16 …rch=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
17 …rch=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
18 …rch=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
19 …rch=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
26 …6 -asm-show-inst -disable-mips-delay-filler < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,R6C
/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/Mips/llvm-ir/
H A Dret.ll15 …rch=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
16 …rch=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
17 …rch=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
18 …rch=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
19 …rch=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
26 …6 -asm-show-inst -disable-mips-delay-filler < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,R6C
/dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/Mips/llvm-ir/
H A Dret.ll15 …rch=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
16 …rch=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
17 …rch=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
18 …rch=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
19 …rch=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
26 …6 -asm-show-inst -disable-mips-delay-filler < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,R6C
/dports/devel/llvm70/llvm-7.0.1.src/test/CodeGen/Mips/llvm-ir/
H A Dret.ll15 …rch=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
16 …rch=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
17 …rch=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
18 …rch=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
19 …rch=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
26 …6 -asm-show-inst -disable-mips-delay-filler < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,R6C
/dports/lang/v8/v8-9.6.180.12/src/compiler/backend/mips64/
H A Dinstruction-scheduler-mips64.cc537 DMTC1 = 4, enumerator
838 return UldLatency() + Latency::DMTC1; in Uldc1Latency()
1106 Latency::DMFC1 + 1 + XorLatency() + Latency::DMTC1; in NegdLatency()
1204 3 * Latency::DMFC1 + OrLatency() + Latency::DMTC1 + Latency::MOV_D + in TruncUlDLatency()
1563 return 1 + Latency::DMTC1 + Latency::CVT_S_L; in GetInstructionLatency()
1565 return Latency::DMTC1 + Latency::CVT_S_L; in GetInstructionLatency()
1567 return Latency::DMTC1 + Latency::CVT_D_L; in GetInstructionLatency()
1569 return 1 + Latency::DMTC1 + Latency::CVT_D_L; in GetInstructionLatency()
1571 return 2 * Latency::BRANCH + 3 + 2 * Latency::DMTC1 + in GetInstructionLatency()
1574 return 2 * Latency::BRANCH + 3 + 2 * Latency::DMTC1 + in GetInstructionLatency()
[all …]
/dports/www/qt5-webengine/qtwebengine-everywhere-src-5.15.2/src/3rdparty/chromium/v8/src/compiler/backend/mips64/
H A Dinstruction-scheduler-mips64.cc526 DMTC1 = 4, enumerator
832 return UldLatency() + Latency::DMTC1; in Uldc1Latency()
1100 Latency::DMFC1 + 1 + XorLatency() + Latency::DMTC1; in NegdLatency()
1198 3 * Latency::DMFC1 + OrLatency() + Latency::DMTC1 + Latency::MOV_D + in TruncUlDLatency()
1565 return 1 + Latency::DMTC1 + Latency::CVT_S_L; in GetInstructionLatency()
1567 return Latency::DMTC1 + Latency::CVT_S_L; in GetInstructionLatency()
1569 return Latency::DMTC1 + Latency::CVT_D_L; in GetInstructionLatency()
1571 return 1 + Latency::DMTC1 + Latency::CVT_D_L; in GetInstructionLatency()
1573 return 2 * Latency::BRANCH + 3 + 2 * Latency::DMTC1 + in GetInstructionLatency()
1576 return 2 * Latency::BRANCH + 3 + 2 * Latency::DMTC1 + in GetInstructionLatency()
[all …]
/dports/www/chromium-legacy/chromium-88.0.4324.182/v8/src/compiler/backend/mips64/
H A Dinstruction-scheduler-mips64.cc549 DMTC1 = 4, enumerator
855 return UldLatency() + Latency::DMTC1; in Uldc1Latency()
1123 Latency::DMFC1 + 1 + XorLatency() + Latency::DMTC1; in NegdLatency()
1221 3 * Latency::DMFC1 + OrLatency() + Latency::DMTC1 + Latency::MOV_D + in TruncUlDLatency()
1588 return 1 + Latency::DMTC1 + Latency::CVT_S_L; in GetInstructionLatency()
1590 return Latency::DMTC1 + Latency::CVT_S_L; in GetInstructionLatency()
1592 return Latency::DMTC1 + Latency::CVT_D_L; in GetInstructionLatency()
1594 return 1 + Latency::DMTC1 + Latency::CVT_D_L; in GetInstructionLatency()
1596 return 2 * Latency::BRANCH + 3 + 2 * Latency::DMTC1 + in GetInstructionLatency()
1599 return 2 * Latency::BRANCH + 3 + 2 * Latency::DMTC1 + in GetInstructionLatency()
[all …]
/dports/games/libretro-paralleln64/parallel-n64-6e26fbb/mupen64plus-core/src/r4300/
H A Dops.h216 void (*DMTC1)(void); member
H A Dcached_interp.c415 DMTC1,
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp161 Opc = Mips::DMTC1; in copyPhysReg()
410 BuildMI(MBB, I, DL, get(Mips::DMTC1), DestReg) in loadRegFromStack()
559 expandCvtFPInt(MBB, MI, Mips::CVT_S_L, Mips::DMTC1, true); in expandPostRAPseudo()
566 expandCvtFPInt(MBB, MI, Mips::CVT_D64_L, Mips::DMTC1, true); in expandPostRAPseudo()
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp165 Opc = Mips::DMTC1; in copyPhysReg()
455 expandCvtFPInt(MBB, MI, Mips::CVT_S_L, Mips::DMTC1, true); in expandPostRAPseudo()
462 expandCvtFPInt(MBB, MI, Mips::CVT_D64_L, Mips::DMTC1, true); in expandPostRAPseudo()
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp165 Opc = Mips::DMTC1; in copyPhysReg()
455 expandCvtFPInt(MBB, MI, Mips::CVT_S_L, Mips::DMTC1, true); in expandPostRAPseudo()
462 expandCvtFPInt(MBB, MI, Mips::CVT_D64_L, Mips::DMTC1, true); in expandPostRAPseudo()
/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp165 Opc = Mips::DMTC1; in copyPhysReg()
455 expandCvtFPInt(MBB, MI, Mips::CVT_S_L, Mips::DMTC1, true); in expandPostRAPseudo()
462 expandCvtFPInt(MBB, MI, Mips::CVT_D64_L, Mips::DMTC1, true); in expandPostRAPseudo()
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp165 Opc = Mips::DMTC1;
455 expandCvtFPInt(MBB, MI, Mips::CVT_S_L, Mips::DMTC1, true);
462 expandCvtFPInt(MBB, MI, Mips::CVT_D64_L, Mips::DMTC1, true);

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