/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/arm/mach-sunxi/dram_timings/ |
H A D | ddr2_v3s.c | 67 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
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H A D | lpddr3_stock.c | 66 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
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H A D | ddr3_1333.c | 70 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
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/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/arm/mach-sunxi/dram_timings/ |
H A D | ddr2_v3s.c | 67 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
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H A D | ddr3_1333.c | 70 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
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H A D | lpddr3_stock.c | 66 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
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/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/mach-sunxi/dram_timings/ |
H A D | lpddr3_stock.c | 66 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
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H A D | ddr2_v3s.c | 67 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
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H A D | ddr3_1333.c | 70 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
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/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/arm/mach-sunxi/dram_timings/ |
H A D | ddr3_1333.c | 70 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
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H A D | ddr2_v3s.c | 67 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
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H A D | lpddr3_stock.c | 66 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
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/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/mach-sunxi/dram_timings/ |
H A D | ddr2_v3s.c | 67 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
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H A D | ddr3_1333.c | 70 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
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H A D | lpddr3_stock.c | 66 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
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/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/arm/mach-sunxi/dram_timings/ |
H A D | ddr2_v3s.c | 67 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
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/dports/sysutils/u-boot-chip/u-boot-2021.07/arch/arm/mach-sunxi/dram_timings/ |
H A D | ddr2_v3s.c | 67 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
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H A D | ddr3_1333.c | 70 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
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H A D | lpddr3_stock.c | 66 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
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/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/mach-sunxi/dram_timings/ |
H A D | ddr3_1333.c | 70 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
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H A D | ddr2_v3s.c | 67 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
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H A D | lpddr3_stock.c | 66 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
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/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/arch/arm/mach-sunxi/dram_timings/ |
H A D | ddr3_1333.c | 70 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
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H A D | ddr2_v3s.c | 67 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
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/dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/arm/mach-sunxi/dram_timings/ |
H A D | ddr2_v3s.c | 67 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
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