| /dports/devel/codeblocks/codeblocks-20.03/src/plugins/scriptedwizard/resources/arm/files/phyCORE-PXA255/h/ |
| H A D | pxa255regs.h | 87 #define DRCMR5 __REG(DMA_CTL_BASE+0x0114) /* Request to Channel Map Register for BTUART transmit… macro
126 #define DRCMRTXBTTHR DRCMR5
|
| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/arm/include/asm/arch-pxa/ |
| H A D | pxa-regs.h | 160 #define DRCMR5 0x40000114 /* Request to Channel Map Register for BTUART transmit Request. */ macro
203 #define DRCMRTXBTTHR DRCMR5
|
| /dports/emulators/qemu/qemu-6.2.0/roms/u-boot/arch/arm/include/asm/arch-pxa/ |
| H A D | pxa-regs.h | 160 #define DRCMR5 0x40000114 /* Request to Channel Map Register for BTUART transmit Request. */ macro
203 #define DRCMRTXBTTHR DRCMR5
|
| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/arm/include/asm/arch-pxa/ |
| H A D | pxa-regs.h | 160 #define DRCMR5 0x40000114 /* Request to Channel Map Register for BTUART transmit Request. */ macro
203 #define DRCMRTXBTTHR DRCMR5
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/include/asm/arch-pxa/ |
| H A D | pxa-regs.h | 160 #define DRCMR5 0x40000114 /* Request to Channel Map Register for BTUART transmit Request. */ macro
203 #define DRCMRTXBTTHR DRCMR5
|
| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/include/asm/arch-pxa/ |
| H A D | pxa-regs.h | 160 #define DRCMR5 0x40000114 /* Request to Channel Map Register for BTUART transmit Request. */ macro
203 #define DRCMRTXBTTHR DRCMR5
|
| /dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/arm/include/asm/arch-pxa/ |
| H A D | pxa-regs.h | 160 #define DRCMR5 0x40000114 /* Request to Channel Map Register for BTUART transmit Request. */ macro
203 #define DRCMRTXBTTHR DRCMR5
|
| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/include/asm/arch-pxa/ |
| H A D | pxa-regs.h | 160 #define DRCMR5 0x40000114 /* Request to Channel Map Register for BTUART transmit Request. */ macro
203 #define DRCMRTXBTTHR DRCMR5
|
| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/include/asm/arch-pxa/ |
| H A D | pxa-regs.h | 160 #define DRCMR5 0x40000114 /* Request to Channel Map Register for BTUART transmit Request. */ macro
203 #define DRCMRTXBTTHR DRCMR5
|
| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/arch/arm/include/asm/arch-pxa/ |
| H A D | pxa-regs.h | 160 #define DRCMR5 0x40000114 /* Request to Channel Map Register for BTUART transmit Request. */ macro
203 #define DRCMRTXBTTHR DRCMR5
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/include/asm/arch-pxa/ |
| H A D | pxa-regs.h | 160 #define DRCMR5 0x40000114 /* Request to Channel Map Register for BTUART transmit Request. */ macro
203 #define DRCMRTXBTTHR DRCMR5
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/arm/include/asm/arch-pxa/ |
| H A D | pxa-regs.h | 160 #define DRCMR5 0x40000114 /* Request to Channel Map Register for BTUART transmit Request. */ macro
203 #define DRCMRTXBTTHR DRCMR5
|
| /dports/sysutils/u-boot-bananapi/u-boot-2021.07/arch/arm/include/asm/arch-pxa/ |
| H A D | pxa-regs.h | 160 #define DRCMR5 0x40000114 /* Request to Channel Map Register for BTUART transmit Request. */ macro
203 #define DRCMRTXBTTHR DRCMR5
|
| /dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/arm/include/asm/arch-pxa/ |
| H A D | pxa-regs.h | 160 #define DRCMR5 0x40000114 /* Request to Channel Map Register for BTUART transmit Request. */ macro
203 #define DRCMRTXBTTHR DRCMR5
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/arm/include/asm/arch-pxa/ |
| H A D | pxa-regs.h | 160 #define DRCMR5 0x40000114 /* Request to Channel Map Register for BTUART transmit Request. */ macro
203 #define DRCMRTXBTTHR DRCMR5
|
| /dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/arm/include/asm/arch-pxa/ |
| H A D | pxa-regs.h | 160 #define DRCMR5 0x40000114 /* Request to Channel Map Register for BTUART transmit Request. */ macro
203 #define DRCMRTXBTTHR DRCMR5
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/arm/include/asm/arch-pxa/ |
| H A D | pxa-regs.h | 160 #define DRCMR5 0x40000114 /* Request to Channel Map Register for BTUART transmit Request. */ macro
203 #define DRCMRTXBTTHR DRCMR5
|
| /dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/arm/include/asm/arch-pxa/ |
| H A D | pxa-regs.h | 160 #define DRCMR5 0x40000114 /* Request to Channel Map Register for BTUART transmit Request. */ macro
203 #define DRCMRTXBTTHR DRCMR5
|
| /dports/sysutils/u-boot-nanopi-a64/u-boot-2021.07/arch/arm/include/asm/arch-pxa/ |
| H A D | pxa-regs.h | 160 #define DRCMR5 0x40000114 /* Request to Channel Map Register for BTUART transmit Request. */ macro
203 #define DRCMRTXBTTHR DRCMR5
|
| /dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/arch/arm/include/asm/arch-pxa/ |
| H A D | pxa-regs.h | 160 #define DRCMR5 0x40000114 /* Request to Channel Map Register for BTUART transmit Request. */ macro
203 #define DRCMRTXBTTHR DRCMR5
|
| /dports/sysutils/u-boot-nanopi-neo2/u-boot-2021.07/arch/arm/include/asm/arch-pxa/ |
| H A D | pxa-regs.h | 160 #define DRCMR5 0x40000114 /* Request to Channel Map Register for BTUART transmit Request. */ macro
203 #define DRCMRTXBTTHR DRCMR5
|
| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/arm/include/asm/arch-pxa/ |
| H A D | pxa-regs.h | 160 #define DRCMR5 0x40000114 /* Request to Channel Map Register for BTUART transmit Request. */ macro
203 #define DRCMRTXBTTHR DRCMR5
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/arm/include/asm/arch-pxa/ |
| H A D | pxa-regs.h | 160 #define DRCMR5 0x40000114 /* Request to Channel Map Register for BTUART transmit Request. */
203 #define DRCMRTXBTTHR DRCMR5
|
| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/arm/include/asm/arch-pxa/ |
| H A D | pxa-regs.h | 160 #define DRCMR5 0x40000114 /* Request to Channel Map Register for BTUART transmit Request. */ macro
203 #define DRCMRTXBTTHR DRCMR5
|
| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/arm/include/asm/arch-pxa/ |
| H A D | pxa-regs.h | 160 #define DRCMR5 0x40000114 /* Request to Channel Map Register for BTUART transmit Request. */ macro
203 #define DRCMRTXBTTHR DRCMR5
|