/dports/emulators/qemu42/qemu-4.2.1/hw/dma/ |
H A D | pxa2xx_dma.c | 84 #define DRCMR_MAPVLD (1 << 7) macro 341 if (value & DRCMR_MAPVLD) in pxa2xx_dma_write() 440 if (!(s->req[req_num] & DRCMR_MAPVLD)) in pxa2xx_dma_request()
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/dports/emulators/qemu/qemu-6.2.0/hw/dma/ |
H A D | pxa2xx_dma.c | 86 #define DRCMR_MAPVLD (1 << 7) macro 345 if (value & DRCMR_MAPVLD) in pxa2xx_dma_write() 445 if (!(s->req[req_num] & DRCMR_MAPVLD)) in pxa2xx_dma_request()
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/dports/emulators/qemu60/qemu-6.0.0/hw/dma/ |
H A D | pxa2xx_dma.c | 86 #define DRCMR_MAPVLD (1 << 7) macro 345 if (value & DRCMR_MAPVLD) in pxa2xx_dma_write() 445 if (!(s->req[req_num] & DRCMR_MAPVLD)) in pxa2xx_dma_request()
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/dports/emulators/qemu-utils/qemu-4.2.1/hw/dma/ |
H A D | pxa2xx_dma.c | 84 #define DRCMR_MAPVLD (1 << 7) macro 341 if (value & DRCMR_MAPVLD) in pxa2xx_dma_write() 440 if (!(s->req[req_num] & DRCMR_MAPVLD)) in pxa2xx_dma_request()
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/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/hw/dma/ |
H A D | pxa2xx_dma.c | 80 #define DRCMR_MAPVLD (1 << 7) macro 337 if (value & DRCMR_MAPVLD) in pxa2xx_dma_write() 436 if (!(s->req[req_num] & DRCMR_MAPVLD)) in pxa2xx_dma_request()
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/dports/emulators/qemu5/qemu-5.2.0/hw/dma/ |
H A D | pxa2xx_dma.c | 86 #define DRCMR_MAPVLD (1 << 7) macro 345 if (value & DRCMR_MAPVLD) in pxa2xx_dma_write() 445 if (!(s->req[req_num] & DRCMR_MAPVLD)) in pxa2xx_dma_request()
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/hw/dma/ |
H A D | pxa2xx_dma.c | 84 #define DRCMR_MAPVLD (1 << 7) macro 341 if (value & DRCMR_MAPVLD) in pxa2xx_dma_write() 440 if (!(s->req[req_num] & DRCMR_MAPVLD)) in pxa2xx_dma_request()
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/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/hw/dma/ |
H A D | pxa2xx_dma.c | 84 #define DRCMR_MAPVLD (1 << 7) macro 341 if (value & DRCMR_MAPVLD) in pxa2xx_dma_write() 440 if (!(s->req[req_num] & DRCMR_MAPVLD)) in pxa2xx_dma_request()
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/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/hw/dma/ |
H A D | pxa2xx_dma.c | 86 #define DRCMR_MAPVLD (1 << 7) macro 345 if (value & DRCMR_MAPVLD) in pxa2xx_dma_write() 445 if (!(s->req[req_num] & DRCMR_MAPVLD)) in pxa2xx_dma_request()
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/dports/devel/openwince-include/include-0.4.2/arm/pxa2x0/ |
H A D | dma.h | 236 #define DRCMR_MAPVLD bit(7) macro
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/dports/multimedia/libv4l/linux-5.13-rc2/drivers/dma/ |
H A D | pxa_dma.c | 52 #define DRCMR_MAPVLD BIT(7) /* Map Valid (read / write) */ macro 199 !!(drcmr & DRCMR_MAPVLD)); in requester_chan_show() 465 writel_relaxed(DRCMR_MAPVLD | phy->idx, phy->base + reg); in phy_enable()
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H A D | mmp_pdma.c | 50 #define DRCMR_MAPVLD BIT(7) /* Map Valid (read / write) */ macro 159 writel(DRCMR_MAPVLD | phy->idx, phy->base + reg); in enable_chan()
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/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/dma/ |
H A D | pxa_dma.c | 52 #define DRCMR_MAPVLD BIT(7) /* Map Valid (read / write) */ macro 199 !!(drcmr & DRCMR_MAPVLD)); in requester_chan_show() 465 writel_relaxed(DRCMR_MAPVLD | phy->idx, phy->base + reg); in phy_enable()
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H A D | mmp_pdma.c | 50 #define DRCMR_MAPVLD BIT(7) /* Map Valid (read / write) */ macro 159 writel(DRCMR_MAPVLD | phy->idx, phy->base + reg); in enable_chan()
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/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/dma/ |
H A D | pxa_dma.c | 52 #define DRCMR_MAPVLD BIT(7) /* Map Valid (read / write) */ macro 199 !!(drcmr & DRCMR_MAPVLD)); in requester_chan_show() 465 writel_relaxed(DRCMR_MAPVLD | phy->idx, phy->base + reg); in phy_enable()
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H A D | mmp_pdma.c | 50 #define DRCMR_MAPVLD BIT(7) /* Map Valid (read / write) */ macro 159 writel(DRCMR_MAPVLD | phy->idx, phy->base + reg); in enable_chan()
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/dports/devel/codeblocks/codeblocks-20.03/src/plugins/scriptedwizard/resources/arm/files/phyCORE-PXA255/h/ |
H A D | pxa255regs.h | 143 #define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */ macro
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/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/arm/include/asm/arch-pxa/ |
H A D | pxa-regs.h | 220 #define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */ macro
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/dports/emulators/qemu/qemu-6.2.0/roms/u-boot/arch/arm/include/asm/arch-pxa/ |
H A D | pxa-regs.h | 220 #define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */ macro
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/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/arm/include/asm/arch-pxa/ |
H A D | pxa-regs.h | 220 #define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */ macro
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/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/include/asm/arch-pxa/ |
H A D | pxa-regs.h | 220 #define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */ macro
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/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/include/asm/arch-pxa/ |
H A D | pxa-regs.h | 220 #define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */ macro
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/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/arm/include/asm/arch-pxa/ |
H A D | pxa-regs.h | 220 #define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */ macro
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/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/include/asm/arch-pxa/ |
H A D | pxa-regs.h | 220 #define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */ macro
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/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/include/asm/arch-pxa/ |
H A D | pxa-regs.h | 220 #define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */ macro
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