| /dports/cad/yosys/yosys-yosys-0.12/techlibs/ice40/tests/ |
| H A D | test_dsp_model.v | 8 parameter [0:0] D_REG = 0; constant
121 .D_REG (D_REG ),
172 .D_REG (D_REG ),
225 .D_REG (0),
250 .D_REG (0),
275 .D_REG (0),
300 .D_REG (0),
325 .D_REG (0),
350 .D_REG (0),
375 .D_REG (0),
[all …]
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| /dports/games/uqm/uqm-0.8.0/src/libs/graphics/sdl/ |
| H A D | scalemmx.h | 494 # define D_REG "rdx" macro
498 # define D_REG "edx" macro
632 CLR_UPPER32 (D_REG) "\n\t" in SCALE_()
644 "movd (%3, %%" D_REG ", 4), %%mm2 \n\t" in SCALE_()
673 : "%" A_REG, "%" D_REG, "cc" in SCALE_()
697 CLR_UPPER32(D_REG) "\n\t" in SCALE_()
705 "or %%" D_REG ", %%" D_REG "\n\t" in SCALE_()
712 : "%" D_REG, "cc" in SCALE_()
788 #undef D_REG
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| /dports/cad/yosys/yosys-yosys-0.12/techlibs/ice40/ |
| H A D | dsp_map.v | 13 .D_REG(1'b0),
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| /dports/devel/icestorm/icestorm-710470f9/icefuzz/tests/ |
| H A D | sb_mac16.v | 59 defparam i_sbmac16. D_REG = 1'b0;
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| /dports/emulators/bochs/bochs-2.7/gui/ |
| H A D | enh_dbg.h | 114 #define D_REG 17 macro
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| H A D | gtk_enh_dbg_osdep.cc | 344 ChkMIs[D_REG] = gtk_check_menu_item_new_with_label("Show Debug Registers\t\tShift+F4"); in InitMenus()
415 gtk_menu_shell_append(GTK_MENU_SHELL(OptMenu), ChkMIs[D_REG]); in InitMenus()
436 gtk_check_menu_item_set_active(GTK_CHECK_MENU_ITEM(ChkMIs[D_REG]), SeeReg[6]); in InitMenus()
1776 … g_signal_connect (G_OBJECT(ChkMIs[D_REG]), "activate", G_CALLBACK(nbCmd_cb), (gpointer) CMD_DREG); in AttachSignals()
1777 Cmd2MI[CMD_DREG - CMD_IDX_LO + 1] = ChkMIs[D_REG]; in AttachSignals()
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| /dports/cad/yosys/yosys-yosys-0.12/techlibs/xilinx/ |
| H A D | cells_sim.v | 2735 reg signed [17:0] D_REG; register
2748 D_REG = 0;
2789 D_REG <= 0;
2791 D_REG <= D;
2859 D_REG <= 0;
2861 D_REG <= D;
2908 assign D_OUT = (DREG == 1) ? D_REG : D;
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| /dports/lang/gcc48/gcc-4.8.5/gcc/config/rl78/ |
| H A D | rl78.md | 31 (D_REG 5)
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| /dports/devel/mingw32-gcc/gcc-4.8.1/gcc/config/rl78/ |
| H A D | rl78.md | 31 (D_REG 5)
|
| /dports/multimedia/libv4l/linux-5.13-rc2/drivers/clk/qcom/ |
| H A D | clk-rcg2.c | 43 #define D_REG 0x10 macro
48 #define RCG_D_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + D_REG)
|
| /dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/clk/qcom/ |
| H A D | clk-rcg2.c | 43 #define D_REG 0x10 macro
48 #define RCG_D_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + D_REG)
|
| /dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/clk/qcom/ |
| H A D | clk-rcg2.c | 43 #define D_REG 0x10 macro
48 #define RCG_D_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + D_REG)
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| /dports/cad/yosys/yosys-yosys-0.12/passes/pmgen/ |
| H A D | ice40_dsp.cc | 97 cell->setParam(ID(D_REG), st.ffCD ? State::S1 : State::S0); in create_ice40_dsp()
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| H A D | ice40_dsp.pmg | 269 (mul->type != \SB_MAC16 || (!param(mul, \C_REG).as_bool() && !param(mul, \D_REG).as_bool()))) {
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| /dports/devel/arm-none-eabi-gcc492/gcc-4.9.2/gcc/config/rl78/ |
| H A D | rl78.md | 31 (D_REG 5)
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| /dports/lang/gcc6-aux/gcc-6-20180516/gcc/config/rl78/ |
| H A D | rl78.c | 2584 #define D gen_rtx_REG (QImode, D_REG)
3921 || i == D_REG in set_origin()
3925 || origins[i] == D_REG in set_origin()
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| /dports/lang/gnat_util/gcc-6-20180516/gcc/config/rl78/ |
| H A D | rl78.c | 2584 #define D gen_rtx_REG (QImode, D_REG)
3921 || i == D_REG in set_origin()
3925 || origins[i] == D_REG in set_origin()
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| /dports/devel/aarch64-none-elf-gcc/gcc-8.4.0/gcc/config/rl78/ |
| H A D | rl78.c | 2791 #define D gen_rtx_REG (QImode, D_REG)
4135 || i == D_REG in set_origin()
4139 || origins[i] == D_REG in set_origin()
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| /dports/lang/gcc9/gcc-9.4.0/gcc/config/rl78/ |
| H A D | rl78.c | 2802 #define D gen_rtx_REG (QImode, D_REG)
4146 || i == D_REG in set_origin()
4150 || origins[i] == D_REG in set_origin()
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| /dports/devel/avr-gcc/gcc-10.2.0/gcc/config/rl78/ |
| H A D | rl78.c | 2791 #define D gen_rtx_REG (QImode, D_REG)
4135 || i == D_REG in set_origin()
4139 || origins[i] == D_REG in set_origin()
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| /dports/devel/riscv64-gcc/gcc-8.3.0/gcc/config/rl78/ |
| H A D | rl78.c | 2791 #define D gen_rtx_REG (QImode, D_REG)
4135 || i == D_REG in set_origin()
4139 || origins[i] == D_REG in set_origin()
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| /dports/lang/gcc11-devel/gcc-11-20211009/gcc/config/rl78/ |
| H A D | rl78.c | 2791 #define D gen_rtx_REG (QImode, D_REG)
4135 || i == D_REG in set_origin()
4139 || origins[i] == D_REG in set_origin()
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| /dports/lang/gcc12-devel/gcc-12-20211205/gcc/config/rl78/ |
| H A D | rl78.c | 2791 #define D gen_rtx_REG (QImode, D_REG)
4134 || i == D_REG in set_origin()
4138 || origins[i] == D_REG in set_origin()
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| /dports/devel/riscv32-unknown-elf-gcc/gcc-8.4.0/gcc/config/rl78/ |
| H A D | rl78.c | 2791 #define D gen_rtx_REG (QImode, D_REG)
4135 || i == D_REG in set_origin()
4139 || origins[i] == D_REG in set_origin()
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| /dports/devel/arm-none-eabi-gcc/gcc-8.4.0/gcc/config/rl78/ |
| H A D | rl78.c | 2791 #define D gen_rtx_REG (QImode, D_REG)
4135 || i == D_REG in set_origin()
4139 || origins[i] == D_REG in set_origin()
|