/dports/games/zdoom/zdoom-2.8.1/src/ |
H A D | gccinlines.h | 217 static inline SDWORD DivScale1 (SDWORD a, SDWORD b) in DivScale1() function
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H A D | mscinlines.h | 267 __forceinline SDWORD DivScale1 (SDWORD a, SDWORD b) in DivScale1() function
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H A D | basicinlines.h | 147 static inline SDWORD DivScale1 (SDWORD a, SDWORD b) { return (SDWORD)(((SQWORD)a << 1) / b); } in DivScale1() function
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/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPULegalizerInfo.cpp | 2160 auto DivScale1 = B.buildIntrinsic(Intrinsic::amdgcn_div_scale, {S64, S1}, false) in legalizeFDIV64() local 2167 auto Mul = B.buildMul(S64, DivScale1.getReg(0), Fma3, Flags); in legalizeFDIV64() 2168 auto Fma4 = B.buildFMA(S64, NegDivScale0, Mul, DivScale1.getReg(0), Flags); in legalizeFDIV64() 2182 auto Scale1Unmerge = B.buildUnmerge(S32, DivScale1); in legalizeFDIV64() 2190 Scale = DivScale1.getReg(1); in legalizeFDIV64()
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H A D | SIISelLowering.cpp | 7831 SDValue DivScale1 = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT, X, Y, X); in LowerFDIV64() local 7834 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, DivScale1, Fma3); in LowerFDIV64() 7837 NegDivScale0, Mul, DivScale1); in LowerFDIV64() 7851 SDValue Scale1BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, DivScale1); in LowerFDIV64() 7865 Scale = DivScale1.getValue(1); in LowerFDIV64()
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/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/AMDGPU/ |
H A D | AMDGPULegalizerInfo.cpp | 2160 auto DivScale1 = B.buildIntrinsic(Intrinsic::amdgcn_div_scale, {S64, S1}, false) in legalizeFDIV64() local 2167 auto Mul = B.buildMul(S64, DivScale1.getReg(0), Fma3, Flags); in legalizeFDIV64() 2168 auto Fma4 = B.buildFMA(S64, NegDivScale0, Mul, DivScale1.getReg(0), Flags); in legalizeFDIV64() 2182 auto Scale1Unmerge = B.buildUnmerge(S32, DivScale1); in legalizeFDIV64() 2190 Scale = DivScale1.getReg(1); in legalizeFDIV64()
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H A D | SIISelLowering.cpp | 7831 SDValue DivScale1 = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT, X, Y, X); in LowerFDIV64() local 7834 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, DivScale1, Fma3); in LowerFDIV64() 7837 NegDivScale0, Mul, DivScale1); in LowerFDIV64() 7851 SDValue Scale1BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, DivScale1); in LowerFDIV64() 7865 Scale = DivScale1.getValue(1); in LowerFDIV64()
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPULegalizerInfo.cpp | 2160 auto DivScale1 = B.buildIntrinsic(Intrinsic::amdgcn_div_scale, {S64, S1}, false) in legalizeFDIV64() local 2167 auto Mul = B.buildMul(S64, DivScale1.getReg(0), Fma3, Flags); in legalizeFDIV64() 2168 auto Fma4 = B.buildFMA(S64, NegDivScale0, Mul, DivScale1.getReg(0), Flags); in legalizeFDIV64() 2182 auto Scale1Unmerge = B.buildUnmerge(S32, DivScale1); in legalizeFDIV64() 2190 Scale = DivScale1.getReg(1); in legalizeFDIV64()
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H A D | SIISelLowering.cpp | 7831 SDValue DivScale1 = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT, X, Y, X); in LowerFDIV64() local 7834 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, DivScale1, Fma3); in LowerFDIV64() 7837 NegDivScale0, Mul, DivScale1); in LowerFDIV64() 7851 SDValue Scale1BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, DivScale1); in LowerFDIV64() 7865 Scale = DivScale1.getValue(1); in LowerFDIV64()
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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPULegalizerInfo.cpp | 3029 auto DivScale1 = B.buildIntrinsic(Intrinsic::amdgcn_div_scale, {S64, S1}, false) in legalizeFDIV64() local 3036 auto Mul = B.buildFMul(S64, DivScale1.getReg(0), Fma3, Flags); in legalizeFDIV64() 3037 auto Fma4 = B.buildFMA(S64, NegDivScale0, Mul, DivScale1.getReg(0), Flags); in legalizeFDIV64() 3049 auto Scale1Unmerge = B.buildUnmerge(S32, DivScale1); in legalizeFDIV64() 3057 Scale = DivScale1.getReg(1); in legalizeFDIV64()
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H A D | SIISelLowering.cpp | 8298 SDValue DivScale1 = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT, X, Y, X); in LowerFDIV64() local 8301 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, DivScale1, Fma3); in LowerFDIV64() 8304 NegDivScale0, Mul, DivScale1); in LowerFDIV64() 8318 SDValue Scale1BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, DivScale1); in LowerFDIV64() 8332 Scale = DivScale1.getValue(1); in LowerFDIV64()
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/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/AMDGPU/ |
H A D | AMDGPULegalizerInfo.cpp | 3029 auto DivScale1 = B.buildIntrinsic(Intrinsic::amdgcn_div_scale, {S64, S1}, false) in legalizeFDIV64() local 3036 auto Mul = B.buildFMul(S64, DivScale1.getReg(0), Fma3, Flags); in legalizeFDIV64() 3037 auto Fma4 = B.buildFMA(S64, NegDivScale0, Mul, DivScale1.getReg(0), Flags); in legalizeFDIV64() 3049 auto Scale1Unmerge = B.buildUnmerge(S32, DivScale1); in legalizeFDIV64() 3057 Scale = DivScale1.getReg(1); in legalizeFDIV64()
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H A D | SIISelLowering.cpp | 8299 SDValue DivScale1 = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT, X, Y, X); in LowerFDIV64() local 8302 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, DivScale1, Fma3); in LowerFDIV64() 8305 NegDivScale0, Mul, DivScale1); in LowerFDIV64() 8319 SDValue Scale1BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, DivScale1); in LowerFDIV64() 8333 Scale = DivScale1.getValue(1); in LowerFDIV64()
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPULegalizerInfo.cpp | 3267 auto DivScale1 = B.buildIntrinsic(Intrinsic::amdgcn_div_scale, {S64, S1}, false) in legalizeFDIV64() local 3274 auto Mul = B.buildFMul(S64, DivScale1.getReg(0), Fma3, Flags); in legalizeFDIV64() 3275 auto Fma4 = B.buildFMA(S64, NegDivScale0, Mul, DivScale1.getReg(0), Flags); in legalizeFDIV64() 3287 auto Scale1Unmerge = B.buildUnmerge(S32, DivScale1); in legalizeFDIV64() 3295 Scale = DivScale1.getReg(1); in legalizeFDIV64()
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPULegalizerInfo.cpp | 3435 auto DivScale1 = B.buildIntrinsic(Intrinsic::amdgcn_div_scale, {S64, S1}, false) in legalizeFDIV64() local 3442 auto Mul = B.buildFMul(S64, DivScale1.getReg(0), Fma3, Flags); in legalizeFDIV64() 3443 auto Fma4 = B.buildFMA(S64, NegDivScale0, Mul, DivScale1.getReg(0), Flags); in legalizeFDIV64() 3455 auto Scale1Unmerge = B.buildUnmerge(S32, DivScale1); in legalizeFDIV64() 3463 Scale = DivScale1.getReg(1); in legalizeFDIV64()
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AMDGPU/ |
H A D | AMDGPULegalizerInfo.cpp | 3435 auto DivScale1 = B.buildIntrinsic(Intrinsic::amdgcn_div_scale, {S64, S1}, false) in legalizeFDIV64() local 3442 auto Mul = B.buildFMul(S64, DivScale1.getReg(0), Fma3, Flags); in legalizeFDIV64() 3443 auto Fma4 = B.buildFMA(S64, NegDivScale0, Mul, DivScale1.getReg(0), Flags); in legalizeFDIV64() 3455 auto Scale1Unmerge = B.buildUnmerge(S32, DivScale1); in legalizeFDIV64() 3463 Scale = DivScale1.getReg(1); in legalizeFDIV64()
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPULegalizerInfo.cpp | 3296 auto DivScale1 = B.buildIntrinsic(Intrinsic::amdgcn_div_scale, {S64, S1}, false) in legalizeFDIV64() local 3303 auto Mul = B.buildFMul(S64, DivScale1.getReg(0), Fma3, Flags); in legalizeFDIV64() 3304 auto Fma4 = B.buildFMA(S64, NegDivScale0, Mul, DivScale1.getReg(0), Flags); in legalizeFDIV64() 3316 auto Scale1Unmerge = B.buildUnmerge(S32, DivScale1); in legalizeFDIV64() 3324 Scale = DivScale1.getReg(1); in legalizeFDIV64()
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/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPULegalizerInfo.cpp | 3435 auto DivScale1 = B.buildIntrinsic(Intrinsic::amdgcn_div_scale, {S64, S1}, false) in legalizeFDIV64() local 3442 auto Mul = B.buildFMul(S64, DivScale1.getReg(0), Fma3, Flags); in legalizeFDIV64() 3443 auto Fma4 = B.buildFMA(S64, NegDivScale0, Mul, DivScale1.getReg(0), Flags); in legalizeFDIV64() 3455 auto Scale1Unmerge = B.buildUnmerge(S32, DivScale1); in legalizeFDIV64() 3463 Scale = DivScale1.getReg(1); in legalizeFDIV64()
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPULegalizerInfo.cpp | 3504 auto DivScale1 = B.buildIntrinsic(Intrinsic::amdgcn_div_scale, {S64, S1}, false) in legalizeFDIV64() local 3511 auto Mul = B.buildFMul(S64, DivScale1.getReg(0), Fma3, Flags); in legalizeFDIV64() 3512 auto Fma4 = B.buildFMA(S64, NegDivScale0, Mul, DivScale1.getReg(0), Flags); in legalizeFDIV64() 3524 auto Scale1Unmerge = B.buildUnmerge(S32, DivScale1); in legalizeFDIV64() 3532 Scale = DivScale1.getReg(1); in legalizeFDIV64()
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPULegalizerInfo.cpp | 3435 auto DivScale1 = B.buildIntrinsic(Intrinsic::amdgcn_div_scale, {S64, S1}, false) in legalizeFDIV64() local 3442 auto Mul = B.buildFMul(S64, DivScale1.getReg(0), Fma3, Flags); in legalizeFDIV64() 3443 auto Fma4 = B.buildFMA(S64, NegDivScale0, Mul, DivScale1.getReg(0), Flags); in legalizeFDIV64() 3455 auto Scale1Unmerge = B.buildUnmerge(S32, DivScale1); in legalizeFDIV64() 3463 Scale = DivScale1.getReg(1); in legalizeFDIV64()
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPULegalizerInfo.cpp | 3296 auto DivScale1 = B.buildIntrinsic(Intrinsic::amdgcn_div_scale, {S64, S1}, false) in legalizeFDIV64() local 3303 auto Mul = B.buildFMul(S64, DivScale1.getReg(0), Fma3, Flags); in legalizeFDIV64() 3304 auto Fma4 = B.buildFMA(S64, NegDivScale0, Mul, DivScale1.getReg(0), Flags); in legalizeFDIV64() 3316 auto Scale1Unmerge = B.buildUnmerge(S32, DivScale1); in legalizeFDIV64() 3324 Scale = DivScale1.getReg(1); in legalizeFDIV64()
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPULegalizerInfo.cpp | 3435 auto DivScale1 = B.buildIntrinsic(Intrinsic::amdgcn_div_scale, {S64, S1}, false) in legalizeFDIV64() local 3442 auto Mul = B.buildFMul(S64, DivScale1.getReg(0), Fma3, Flags); in legalizeFDIV64() 3443 auto Fma4 = B.buildFMA(S64, NegDivScale0, Mul, DivScale1.getReg(0), Flags); in legalizeFDIV64() 3455 auto Scale1Unmerge = B.buildUnmerge(S32, DivScale1); in legalizeFDIV64() 3463 Scale = DivScale1.getReg(1); in legalizeFDIV64()
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/dports/devel/llvm70/llvm-7.0.1.src/lib/Target/AMDGPU/ |
H A D | SIISelLowering.cpp | 5979 SDValue DivScale1 = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT, X, Y, X); 5982 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, DivScale1, Fma3); 5985 NegDivScale0, Mul, DivScale1); 5999 SDValue Scale1BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, DivScale1); 6013 Scale = DivScale1.getValue(1);
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/dports/devel/llvm80/llvm-8.0.1.src/lib/Target/AMDGPU/ |
H A D | SIISelLowering.cpp | 6848 SDValue DivScale1 = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT, X, Y, X); in LowerFDIV64() local 6851 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, DivScale1, Fma3); in LowerFDIV64() 6854 NegDivScale0, Mul, DivScale1); in LowerFDIV64() 6868 SDValue Scale1BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, DivScale1); in LowerFDIV64() 6882 Scale = DivScale1.getValue(1); in LowerFDIV64()
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/dports/devel/llvm90/llvm-9.0.1.src/lib/Target/AMDGPU/ |
H A D | SIISelLowering.cpp | 7615 SDValue DivScale1 = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT, X, Y, X); in LowerFDIV64() local 7618 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, DivScale1, Fma3); in LowerFDIV64() 7621 NegDivScale0, Mul, DivScale1); in LowerFDIV64() 7635 SDValue Scale1BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, DivScale1); in LowerFDIV64() 7649 Scale = DivScale1.getValue(1); in LowerFDIV64()
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