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Searched refs:EDMA3_ICR (Results 1 – 25 of 63) sorted by relevance

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/dports/sysutils/u-boot-utilite/u-boot-2015.07/drivers/dma/
H A Dti-edma3.c28 #define EDMA3_ICR 0x1070 macro
50 __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR); in qedma3_start()
343 icr_base = base + EDMA3_ICR; in edma3_check_for_transfer()
374 __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR); in qedma3_stop()
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/drivers/dma/
H A Dti-edma3.c30 #define EDMA3_ICR 0x1070 macro
60 __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR); in qedma3_start()
353 icr_base = base + EDMA3_ICR; in edma3_check_for_transfer()
384 __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR); in qedma3_stop()
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/dma/
H A Dti-edma3.c31 #define EDMA3_ICR 0x1070 macro
61 __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR); in qedma3_start()
354 icr_base = base + EDMA3_ICR; in edma3_check_for_transfer()
385 __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR); in qedma3_stop()
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/dma/
H A Dti-edma3.c31 #define EDMA3_ICR 0x1070 macro
61 __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR); in qedma3_start()
354 icr_base = base + EDMA3_ICR; in edma3_check_for_transfer()
385 __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR); in qedma3_stop()
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/dma/
H A Dti-edma3.c31 #define EDMA3_ICR 0x1070 macro
61 __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR); in qedma3_start()
354 icr_base = base + EDMA3_ICR; in edma3_check_for_transfer()
385 __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR); in qedma3_stop()
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/drivers/dma/
H A Dti-edma3.c31 #define EDMA3_ICR 0x1070 macro
61 __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR); in qedma3_start()
354 icr_base = base + EDMA3_ICR; in edma3_check_for_transfer()
385 __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR); in qedma3_stop()
/dports/sysutils/u-boot-wandboard/u-boot-2021.07/drivers/dma/
H A Dti-edma3.c31 #define EDMA3_ICR 0x1070 macro
61 __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR); in qedma3_start()
354 icr_base = base + EDMA3_ICR; in edma3_check_for_transfer()
385 __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR); in qedma3_stop()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/drivers/dma/
H A Dti-edma3.c30 #define EDMA3_ICR 0x1070 macro
60 __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR); in qedma3_start()
353 icr_base = base + EDMA3_ICR; in edma3_check_for_transfer()
384 __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR); in qedma3_stop()
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/dma/
H A Dti-edma3.c31 #define EDMA3_ICR 0x1070 macro
61 __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR); in qedma3_start()
354 icr_base = base + EDMA3_ICR; in edma3_check_for_transfer()
385 __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR); in qedma3_stop()
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/dma/
H A Dti-edma3.c31 #define EDMA3_ICR 0x1070 macro
61 __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR); in qedma3_start()
354 icr_base = base + EDMA3_ICR; in edma3_check_for_transfer()
385 __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR); in qedma3_stop()
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/dma/
H A Dti-edma3.c31 #define EDMA3_ICR 0x1070 macro
61 __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR); in qedma3_start()
354 icr_base = base + EDMA3_ICR; in edma3_check_for_transfer()
385 __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR); in qedma3_stop()
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/dma/
H A Dti-edma3.c31 #define EDMA3_ICR 0x1070 macro
61 __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR); in qedma3_start()
354 icr_base = base + EDMA3_ICR; in edma3_check_for_transfer()
385 __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR); in qedma3_stop()
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/dma/
H A Dti-edma3.c31 #define EDMA3_ICR 0x1070 macro
61 __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR); in qedma3_start()
354 icr_base = base + EDMA3_ICR; in edma3_check_for_transfer()
385 __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR); in qedma3_stop()
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/dma/
H A Dti-edma3.c31 #define EDMA3_ICR 0x1070 macro
61 __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR); in qedma3_start()
354 icr_base = base + EDMA3_ICR; in edma3_check_for_transfer()
385 __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR); in qedma3_stop()
/dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/dma/
H A Dti-edma3.c31 #define EDMA3_ICR 0x1070 macro
61 __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR); in qedma3_start()
354 icr_base = base + EDMA3_ICR; in edma3_check_for_transfer()
385 __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR); in qedma3_stop()
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/dma/
H A Dti-edma3.c31 #define EDMA3_ICR 0x1070 macro
61 __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR); in qedma3_start()
354 icr_base = base + EDMA3_ICR; in edma3_check_for_transfer()
385 __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR); in qedma3_stop()
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/dma/
H A Dti-edma3.c31 #define EDMA3_ICR 0x1070 macro
61 __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR); in qedma3_start()
354 icr_base = base + EDMA3_ICR; in edma3_check_for_transfer()
385 __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR); in qedma3_stop()
/dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/dma/
H A Dti-edma3.c31 #define EDMA3_ICR 0x1070 macro
61 __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR); in qedma3_start()
354 icr_base = base + EDMA3_ICR; in edma3_check_for_transfer()
385 __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR); in qedma3_stop()
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/drivers/dma/
H A Dti-edma3.c30 #define EDMA3_ICR 0x1070 macro
60 __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR); in qedma3_start()
353 icr_base = base + EDMA3_ICR; in edma3_check_for_transfer()
384 __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR); in qedma3_stop()
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/dma/
H A Dti-edma3.c31 #define EDMA3_ICR 0x1070 macro
61 __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR); in qedma3_start()
354 icr_base = base + EDMA3_ICR; in edma3_check_for_transfer()
385 __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR); in qedma3_stop()
/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/dma/
H A Dti-edma3.c31 #define EDMA3_ICR 0x1070 macro
61 __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR); in qedma3_start()
354 icr_base = base + EDMA3_ICR; in edma3_check_for_transfer()
385 __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR); in qedma3_stop()
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/drivers/dma/
H A Dti-edma3.c31 #define EDMA3_ICR 0x1070 macro
61 __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR); in qedma3_start()
354 icr_base = base + EDMA3_ICR; in edma3_check_for_transfer()
385 __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR); in qedma3_stop()
/dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/dma/
H A Dti-edma3.c31 #define EDMA3_ICR 0x1070 macro
61 __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR); in qedma3_start()
354 icr_base = base + EDMA3_ICR; in edma3_check_for_transfer()
385 __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR); in qedma3_stop()
/dports/sysutils/u-boot-beaglebone/u-boot-2021.07/drivers/dma/
H A Dti-edma3.c31 #define EDMA3_ICR 0x1070 macro
61 __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR); in qedma3_start()
354 icr_base = base + EDMA3_ICR; in edma3_check_for_transfer()
385 __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR); in qedma3_stop()
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/drivers/dma/
H A Dti-edma3.c30 #define EDMA3_ICR 0x1070 macro
60 __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR); in qedma3_start()
353 icr_base = base + EDMA3_ICR; in edma3_check_for_transfer()
384 __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR); in qedma3_stop()

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