1 /* 2 * The authors hereby grant permission to use, copy, modify, distribute, 3 * and license this software and its documentation for any purpose, provided 4 * that existing copyright notices are retained in all copies and that this 5 * notice is included verbatim in any distributions. No written agreement, 6 * license, or royalty fee is required for any of the authorized uses. 7 * Modifications to this software may be copyrighted by their authors 8 * and need not follow the licensing terms described here, provided that 9 * the new terms are clearly indicated on the first page of each file where 10 * they apply. 11 */ 12 13 /* 14 ** Copyright (C) 2008 Analog Devices Inc., All Rights Reserved. 15 ** 16 ************************************************************************************ 17 ** 18 ** This include file contains a list of macro "defines" to enable the programmer 19 ** to use symbolic names for register-access and bit-manipulation. 20 ** 21 **/ 22 #ifndef _DEF_BF518_H 23 #define _DEF_BF518_H 24 25 /* Include all Core registers and bit definitions */ 26 #include <def_LPBlackfin.h> 27 28 /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF518 */ 29 30 /* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */ 31 #include <defBF51x_base.h> 32 33 #ifdef _MISRA_RULES 34 #pragma diag(push) 35 #pragma diag(suppress:misra_rule_19_4:"macros not strictly following 19.4") 36 #pragma diag(suppress:misra_rule_19_7:"Allow function-like macros") 37 #endif /* _MISRA_RULES */ 38 39 /* The following are the #defines needed by ADSP-BF518 that are not in the common header */ 40 /* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */ 41 42 #define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */ 43 #define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */ 44 #define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */ 45 #define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */ 46 #define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */ 47 #define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */ 48 #define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */ 49 #define EMAC_FLC 0xFFC0301C /* Flow Control Register */ 50 #define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */ 51 #define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */ 52 #define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */ 53 #define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */ 54 #define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */ 55 #define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */ 56 #define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */ 57 #define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */ 58 #define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */ 59 #define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */ 60 #define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */ 61 62 #define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */ 63 #define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */ 64 #define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */ 65 #define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */ 66 #define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */ 67 #define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */ 68 #define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */ 69 #define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */ 70 71 #define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */ 72 #define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */ 73 #define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */ 74 #define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */ 75 #define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */ 76 77 /* EMAC PTP (IEEE 1588) */ 78 79 #define EMAC_PTP_CTL 0xffc030a0 /* PTP Block Control */ 80 #define EMAC_PTP_IE 0xffc030a4 /* PTP Block Interrupt Enable */ 81 #define EMAC_PTP_ISTAT 0xffc030a8 /* PTP Block Interrupt Status */ 82 #define EMAC_PTP_FOFF 0xffc030ac /* PTP Filter offset Register */ 83 #define EMAC_PTP_FV1 0xffc030b0 /* PTP Filter Value Register 1 */ 84 #define EMAC_PTP_FV2 0xffc030b4 /* PTP Filter Value Register 2 */ 85 #define EMAC_PTP_FV3 0xffc030b8 /* PTP Filter Value Register 3 */ 86 #define EMAC_PTP_ADDEND 0xffc030bc /* PTP Addend for Frequency Compensation */ 87 #define EMAC_PTP_ACCR 0xffc030c0 /* PTP Accumulator for Frequency Compensation */ 88 #define EMAC_PTP_OFFSET 0xffc030c4 /* PTP Time Offset Register */ 89 #define EMAC_PTP_TIMELO 0xffc030c8 /* PTP Precision Clock Time Low */ 90 #define EMAC_PTP_TIMEHI 0xffc030cc /* PTP Precision Clock Time High */ 91 #define EMAC_PTP_RXSNAPLO 0xffc030d0 /* PTP Receive Snapshot Register Low */ 92 #define EMAC_PTP_RXSNAPHI 0xffc030d4 /* PTP Receive Snapshot Register High */ 93 #define EMAC_PTP_TXSNAPLO 0xffc030d8 /* PTP Transmit Snapshot Register Low */ 94 #define EMAC_PTP_TXSNAPHI 0xffc030dc /* PTP Transmit Snapshot Register High */ 95 #define EMAC_PTP_ALARMLO 0xffc030e0 /* PTP Alarm time Low */ 96 #define EMAC_PTP_ALARMHI 0xffc030e4 /* PTP Alarm time High */ 97 #define EMAC_PTP_ID_OFF 0xffc030e8 /* PTP Capture ID offset register */ 98 #define EMAC_PTP_ID_SNAP 0xffc030ec /* PTP Capture ID register */ 99 #define EMAC_PTP_PPS_STARTLOP 0xffc030f0 /* PPS Start Time Low */ 100 #define EMAC_PTP_PPS_STARTHIP 0xffc030f4 /* PPS Start Time High */ 101 #define EMAC_PTP_PPS_PERIOD 0xffc030f8 /* PPS Count Register */ 102 103 #define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */ 104 #define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */ 105 #define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */ 106 #define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */ 107 #define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */ 108 #define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */ 109 #define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */ 110 #define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */ 111 #define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */ 112 #define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */ 113 #define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */ 114 #define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */ 115 #define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */ 116 #define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */ 117 #define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */ 118 #define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */ 119 #define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */ 120 #define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */ 121 #define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */ 122 #define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 < x < 128 */ 123 #define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */ 124 #define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */ 125 #define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */ 126 #define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */ 127 128 #define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */ 129 #define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */ 130 #define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */ 131 #define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */ 132 #define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */ 133 #define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */ 134 #define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */ 135 #define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */ 136 #define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */ 137 #define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */ 138 #define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */ 139 #define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */ 140 #define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */ 141 #define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */ 142 #define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */ 143 #define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */ 144 #define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */ 145 #define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 < x < 128 */ 146 #define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */ 147 #define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */ 148 #define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */ 149 #define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */ 150 #define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */ 151 152 /* Listing for IEEE-Supported Count Registers */ 153 154 #define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */ 155 #define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */ 156 #define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */ 157 #define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */ 158 #define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */ 159 #define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */ 160 #define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */ 161 #define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */ 162 #define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */ 163 #define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */ 164 #define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */ 165 #define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */ 166 #define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */ 167 #define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */ 168 #define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */ 169 #define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */ 170 #define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */ 171 #define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */ 172 #define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */ 173 #define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 < x < 128 */ 174 #define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */ 175 #define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */ 176 #define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */ 177 #define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */ 178 179 #define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */ 180 #define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */ 181 #define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */ 182 #define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */ 183 #define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */ 184 #define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */ 185 #define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */ 186 #define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */ 187 #define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */ 188 #define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */ 189 #define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */ 190 #define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */ 191 #define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */ 192 #define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */ 193 #define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */ 194 #define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */ 195 #define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */ 196 #define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 < x < 128 */ 197 #define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */ 198 #define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */ 199 #define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */ 200 #define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */ 201 #define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */ 202 203 204 /* RSI Registers */ 205 206 #define RSI_PWR_CONTROL 0xFFC03800 /* RSI Power Control Register */ 207 /* legacy register name (below) provided for backwards code compatibility */ 208 #define SDH_PWR_CTL RSI_PWR_CONTROL /* SDH Power Control */ 209 #define RSI_CLK_CONTROL 0xFFC03804 /* RSI Clock Control Register */ 210 /* legacy register name (below) provided for backwards code compatibility */ 211 #define SDH_CLK_CTL RSI_CLK_CONTROL /* SDH Clock Control */ 212 #define RSI_ARGUMENT 0xFFC03808 /* RSI Argument Register */ 213 /* legacy register name (below) provided for backwards code compatibility */ 214 #define SDH_ARGUMENT RSI_ARGUMENT /* SDH Argument */ 215 #define RSI_COMMAND 0xFFC0380C /* RSI Command Register */ 216 /* legacy register name (below) provided for backwards code compatibility */ 217 #define SDH_COMMAND RSI_COMMAND /* SDH Command */ 218 #define RSI_RESP_CMD 0xFFC03810 /* RSI Response Command Register */ 219 /* legacy register name (below) provided for backwards code compatibility */ 220 #define SDH_RESP_CMD RSI_RESP_CMD /* SDH Response Command */ 221 #define RSI_RESPONSE0 0xFFC03814 /* RSI Response Register */ 222 /* legacy register name (below) provided for backwards code compatibility */ 223 #define SDH_RESPONSE0 RSI_RESPONSE0 /* SDH Response0 */ 224 #define RSI_RESPONSE1 0xFFC03818 /* RSI Response Register */ 225 /* legacy register name (below) provided for backwards code compatibility */ 226 #define SDH_RESPONSE1 RSI_RESPONSE1 /* SDH Response1 */ 227 #define RSI_RESPONSE2 0xFFC0381C /* RSI Response Register */ 228 /* legacy register name (below) provided for backwards code compatibility */ 229 #define SDH_RESPONSE2 RSI_RESPONSE2 /* SDH Response2 */ 230 #define RSI_RESPONSE3 0xFFC03820 /* RSI Response Register */ 231 /* legacy register name (below) provided for backwards code compatibility */ 232 #define SDH_RESPONSE3 RSI_RESPONSE3 /* SDH Response3 */ 233 #define RSI_DATA_TIMER 0xFFC03824 /* RSI Data Timer Register */ 234 /* legacy register name (below) provided for backwards code compatibility */ 235 #define SDH_DATA_TIMER RSI_DATA_TIMER /* SDH Data Timer */ 236 #define RSI_DATA_LGTH 0xFFC03828 /* RSI Data Length Register */ 237 /* legacy register name (below) provided for backwards code compatibility */ 238 #define SDH_DATA_LGTH RSI_DATA_LGTH /* SDH Data Length */ 239 #define RSI_DATA_CONTROL 0xFFC0382C /* RSI Data Control Register */ 240 /* legacy register name (below) provided for backwards code compatibility */ 241 #define SDH_DATA_CTL RSI_DATA_CONTROL /* SDH Data Control */ 242 #define RSI_DATA_CNT 0xFFC03830 /* RSI Data Counter Register */ 243 /* legacy register name (below) provided for backwards code compatibility */ 244 #define SDH_DATA_CNT RSI_DATA_CNT /* SDH Data Counter */ 245 #define RSI_STATUS 0xFFC03834 /* RSI Status Register */ 246 /* legacy register name (below) provided for backwards code compatibility */ 247 #define SDH_STATUS RSI_STATUS /* SDH Status */ 248 #define RSI_STATUSCL 0xFFC03838 /* RSI Status Clear Register */ 249 /* legacy register name (below) provided for backwards code compatibility */ 250 #define SDH_STATUS_CLR RSI_STATUSCL /* SDH Status Clear */ 251 #define RSI_MASK0 0xFFC0383C /* RSI Interrupt 0 Mask Register */ 252 /* legacy register name (below) provided for backwards code compatibility */ 253 #define SDH_MASK0 RSI_MASK0 /* SDH Interrupt0 Mask */ 254 #define RSI_MASK1 0xFFC03840 /* RSI Interrupt 1 Mask Register */ 255 /* legacy register name (below) provided for backwards code compatibility */ 256 #define SDH_MASK1 RSI_MASK1 /* SDH Interrupt1 Mask */ 257 #define RSI_FIFO_CNT 0xFFC03848 /* RSI FIFO Counter Register */ 258 /* legacy register name (below) provided for backwards code compatibility */ 259 #define SDH_FIFO_CNT RSI_FIFO_CNT /* SDH FIFO Counter */ 260 #define RSI_CEATA_CONTROL 0xFFC0384C /* RSI CEATA Register */ 261 #define RSI_FIFO 0xFFC03880 /* RSI Data FIFO Register */ 262 /* legacy register name (below) provided for backwards code compatibility */ 263 #define SDH_FIFO RSI_FIFO /* SDH Data FIFO */ 264 #define RSI_ESTAT 0xFFC038C0 /* RSI Exception Status Register */ 265 /* legacy register name (below) provided for backwards code compatibility */ 266 #define SDH_E_STATUS RSI_ESTAT /* SDH Exception Status */ 267 #define RSI_EMASK 0xFFC038C4 /* RSI Exception Mask Register */ 268 /* legacy register name (below) provided for backwards code compatibility */ 269 #define SDH_E_MASK RSI_EMASK /* SDH Exception Mask */ 270 #define RSI_CONFIG 0xFFC038C8 /* RSI Configuration Register */ 271 /* legacy register name (below) provided for backwards code compatibility */ 272 #define SDH_CFG RSI_CONFIG /* SDH Configuration */ 273 #define RSI_RD_WAIT_EN 0xFFC038CC /* RSI Read Wait Enable Register */ 274 /* legacy register name (below) provided for backwards code compatibility */ 275 #define SDH_RD_WAIT_EN RSI_RD_WAIT_EN /* SDH Read Wait Enable */ 276 #define RSI_PID0 0xFFC038D0 /* RSI Peripheral ID Register 0 */ 277 /* legacy register name (below) provided for backwards code compatibility */ 278 #define SDH_PID0 RSI_PID0 /* SDH Peripheral Identification0 */ 279 #define RSI_PID1 0xFFC038D4 /* RSI Peripheral ID Register 1 */ 280 /* legacy register name (below) provided for backwards code compatibility */ 281 #define SDH_PID1 RSI_PID1 /* SDH Peripheral Identification1 */ 282 #define RSI_PID2 0xFFC038D8 /* RSI Peripheral ID Register 2 */ 283 /* legacy register name (below) provided for backwards code compatibility */ 284 #define SDH_PID2 RSI_PID2 /* SDH Peripheral Identification2 */ 285 #define RSI_PID3 0xFFC038DC /* RSI Peripheral ID Register 3 */ 286 /* legacy register name (below) provided for backwards code compatibility */ 287 #define SDH_PID3 RSI_PID3 /* SDH Peripheral Identification3 */ 288 /* RSI Registers */ 289 290 291 292 /*********************************************************************************** 293 ** System MMR Register Bits And Macros 294 ** 295 ** Disclaimer: All macros are intended to make C and Assembly code more readable. 296 ** Use these macros carefully, as any that do left shifts for field 297 ** depositing will result in the lower order bits being destroyed. Any 298 ** macro that shifts left to properly position the bit-field should be 299 ** used as part of an OR to initialize a register and NOT as a dynamic 300 ** modifier UNLESS the lower order bits are saved and ORed back in when 301 ** the macro is used. 302 *************************************************************************************/ 303 304 /************************ ETHERNET 10/100 CONTROLLER MASKS ************************/ 305 306 /* EMAC_OPMODE Masks */ 307 308 #define RE 0x00000001 /* Receiver Enable */ 309 #define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */ 310 #define HU 0x00000010 /* Hash Filter Unicast Address */ 311 #define HM 0x00000020 /* Hash Filter Multicast Address */ 312 #define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */ 313 #define PR 0x00000080 /* Promiscuous Mode Enable */ 314 #define IFE 0x00000100 /* Inverse Filtering Enable */ 315 #define DBF 0x00000200 /* Disable Broadcast Frame Reception */ 316 #define PBF 0x00000400 /* Pass Bad Frames Enable */ 317 #define PSF 0x00000800 /* Pass Short Frames Enable */ 318 #define RAF 0x00001000 /* Receive-All Mode */ 319 #define TE 0x00010000 /* Transmitter Enable */ 320 #define DTXPAD 0x00020000 /* Disable Automatic TX Padding */ 321 #define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */ 322 #define DC 0x00080000 /* Deferral Check */ 323 #define BOLMT 0x00300000 /* Back-Off Limit */ 324 #define BOLMT_10 0x00000000 /* 10-bit range */ 325 #define BOLMT_8 0x00100000 /* 8-bit range */ 326 #define BOLMT_4 0x00200000 /* 4-bit range */ 327 #define BOLMT_1 0x00300000 /* 1-bit range */ 328 #define DRTY 0x00400000 /* Disable TX Retry On Collision */ 329 #define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */ 330 #define RMII 0x01000000 /* RMII/MII* Mode */ 331 #define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */ 332 #define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */ 333 #define LB 0x08000000 /* Internal Loopback Enable */ 334 #define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */ 335 336 /* EMAC_STAADD Masks */ 337 338 #define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */ 339 #define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */ 340 #define STADISPRE 0x00000004 /* Disable Preamble Generation */ 341 #define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */ 342 #define REGAD 0x000007C0 /* STA Register Address */ 343 #define PHYAD 0x0000F800 /* PHY Device Address */ 344 345 #ifdef _MISRA_RULES 346 #define SET_REGAD(x) (((x)&0x1Fu)<< 6 ) /* Set STA Register Address */ 347 #define SET_PHYAD(x) (((x)&0x1Fu)<< 11 ) /* Set PHY Device Address */ 348 #else 349 #define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */ 350 #define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */ 351 #endif /* _MISRA_RULES */ 352 353 /* EMAC_STADAT Mask */ 354 355 #define STADATA 0x0000FFFF /* Station Management Data */ 356 357 /* EMAC_FLC Masks */ 358 359 #define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */ 360 #define FLCE 0x00000002 /* Flow Control Enable */ 361 #define PCF 0x00000004 /* Pass Control Frames */ 362 #define BKPRSEN 0x00000008 /* Enable Backpressure */ 363 #define FLCPAUSE 0xFFFF0000 /* Pause Time */ 364 365 #ifdef _MISRA_RULES 366 #define SET_FLCPAUSE(x) (((x)&0xFFFFu)<< 16) /* Set Pause Time */ 367 #else 368 #define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */ 369 #endif /* _MISRA_RULES */ 370 371 /* EMAC_WKUP_CTL Masks */ 372 373 #define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */ 374 #define MPKE 0x00000002 /* Magic Packet Enable */ 375 #define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */ 376 #define GUWKE 0x00000008 /* Global Unicast Wake Enable */ 377 #define MPKS 0x00000020 /* Magic Packet Received Status */ 378 #define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */ 379 380 /* EMAC_WKUP_FFCMD Masks */ 381 382 #define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */ 383 #define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */ 384 #define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */ 385 #define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */ 386 #define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */ 387 #define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */ 388 #define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */ 389 #define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */ 390 391 /* EMAC_WKUP_FFOFF Masks */ 392 393 #define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */ 394 #define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */ 395 #define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */ 396 #define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */ 397 398 #ifdef _MISRA_RULES 399 #define SET_WF0_OFF(x) (((x)&0xFFu)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */ 400 #define SET_WF1_OFF(x) (((x)&0xFFu)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */ 401 #define SET_WF2_OFF(x) (((x)&0xFFu)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */ 402 #define SET_WF3_OFF(x) (((x)&0xFFu)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */ 403 #else 404 #define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */ 405 #define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */ 406 #define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */ 407 #define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */ 408 #endif /* _MISRA_RULES */ 409 410 /* Set ALL Offsets */ 411 #define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3))) 412 413 /* EMAC_WKUP_FFCRC0 Masks */ 414 415 #define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */ 416 #define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */ 417 418 #ifdef _MISRA_RULES 419 #define SET_WF0_CRC(x) (((x)&0xFFFFu)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */ 420 #define SET_WF1_CRC(x) (((x)&0xFFFFu)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */ 421 #else 422 #define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */ 423 #define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */ 424 #endif /* _MISRA_RULES */ 425 426 /* EMAC_WKUP_FFCRC1 Masks */ 427 428 #define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */ 429 #define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */ 430 431 #ifdef _MISRA_RULES 432 #define SET_WF2_CRC(x) (((x)&0xFFFFu)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */ 433 #define SET_WF3_CRC(x) (((x)&0xFFFFu)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */ 434 #else 435 #define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */ 436 #define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */ 437 #endif /* _MISRA_RULES */ 438 439 /* EMAC_SYSCTL Masks */ 440 441 #define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */ 442 #define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */ 443 #define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */ 444 #define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */ 445 446 #ifdef _MISRA_RULES 447 #define SET_MDCDIV(x) (((x)&0x3Fu)<< 8) /* Set MDC Clock Divisor */ 448 #else 449 #define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */ 450 #endif /* _MISRA_RULES */ 451 452 /* EMAC_SYSTAT Masks */ 453 454 #define PHYINT 0x00000001 /* PHY_INT Interrupt Status */ 455 #define MMCINT 0x00000002 /* MMC Counter Interrupt Status */ 456 #define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */ 457 #define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */ 458 #define WAKEDET 0x00000010 /* Wake-Up Detected Status */ 459 #define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */ 460 #define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */ 461 #define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */ 462 463 /* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */ 464 465 #define RX_FRLEN 0x000007FF /* Frame Length In Bytes */ 466 #define RX_COMP 0x00001000 /* RX Frame Complete */ 467 #define RX_OK 0x00002000 /* RX Frame Received With No Errors */ 468 #define RX_LONG 0x00004000 /* RX Frame Too Long Error */ 469 #define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */ 470 #define RX_CRC 0x00010000 /* RX Frame CRC Error */ 471 #define RX_LEN 0x00020000 /* RX Frame Length Error */ 472 #define RX_FRAG 0x00040000 /* RX Frame Fragment Error */ 473 #define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */ 474 #define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */ 475 #define RX_PHY 0x00200000 /* RX Frame PHY Error */ 476 #define RX_LATE 0x00400000 /* RX Frame Late Collision Error */ 477 #define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */ 478 #define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */ 479 #define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */ 480 #define RX_CTL 0x04000000 /* RX Control Frame Indicator */ 481 #define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */ 482 #define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */ 483 #define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */ 484 #define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */ 485 #define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */ 486 487 /* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */ 488 489 #define TX_COMP 0x00000001 /* TX Frame Complete */ 490 #define TX_OK 0x00000002 /* TX Frame Sent With No Errors */ 491 #define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */ 492 #define TX_LATE 0x00000008 /* TX Frame Late Collision Error */ 493 #define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */ 494 #define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */ 495 #define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */ 496 #define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */ 497 #define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */ 498 #define TX_CCNT 0x00000F00 /* TX Frame Collision Count */ 499 #define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */ 500 #define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */ 501 #define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */ 502 #define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */ 503 #define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */ 504 505 /* EMAC_MMC_CTL Masks */ 506 #define RSTC 0x00000001 /* Reset All Counters */ 507 #define CROLL 0x00000002 /* Counter Roll-Over Enable */ 508 #define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */ 509 #define MMCE 0x00000008 /* Enable MMC Counter Operation */ 510 511 /* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */ 512 #define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */ 513 #define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */ 514 #define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */ 515 #define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */ 516 #define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */ 517 #define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */ 518 #define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */ 519 #define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */ 520 #define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */ 521 #define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */ 522 #define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */ 523 #define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */ 524 #define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */ 525 #define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */ 526 #define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */ 527 #define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */ 528 #define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */ 529 #define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */ 530 #define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */ 531 #define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */ 532 #define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */ 533 #define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */ 534 #define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */ 535 #define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */ 536 537 /* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */ 538 539 #define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */ 540 #define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */ 541 #define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */ 542 #define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */ 543 #define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */ 544 #define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */ 545 #define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */ 546 #define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */ 547 #define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */ 548 #define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */ 549 #define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */ 550 #define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */ 551 #define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */ 552 #define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */ 553 #define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */ 554 #define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */ 555 #define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */ 556 #define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */ 557 #define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */ 558 #define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */ 559 #define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */ 560 #define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */ 561 #define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */ 562 563 564 /* Bit masks for EMAC_PTP_CTL */ 565 566 #define EMAC_PTP_CTL_EN 0x1 /* Block Enable */ 567 #define EMAC_PTP_CTL_TL 0x2 /* Time Stamp Lock */ 568 #define EMAC_PTP_CTL_CKS 0xC /* Clock source for the PTP_TSYNC block */ 569 #define EMAC_PTP_CTL_ASEN 0x10 /* Auxiliary Snapshot Enable */ 570 #define EMAC_PTP_CTL_CKDIV 0x60 /* Divider for the selected PTP_CLK output */ 571 #define EMAC_PTP_CTL_PPSEN 0x80 /* Pulse Per Second (PPS) Enable */ 572 #define EMAC_PTP_CTL_EFTM 0x100 /* Ethernet Frame type field compare mask */ 573 #define EMAC_PTP_CTL_IPVM 0x200 /* IP Version field compare mask */ 574 #define EMAC_PTP_CTL_IPTM 0x400 /* IP Type Frame field (Layer 4 protocol) compare mask */ 575 #define EMAC_PTP_CTL_UDPEM 0x800 /* UDP Event port field compare mask */ 576 #define EMAC_PTP_CTL_PTPCM 0x1000 /* PTP Control field compare mask */ 577 #define EMAC_PTP_CTL_CKOEN 0x2000 /* Clock output Enable */ 578 579 /* Bit masks for EMAC_PTP_IE */ 580 581 #define EMAC_PTP_IE_ALIE 0x1 /* Alarm Feature and Interrupt Enable */ 582 #define EMAC_PTP_IE_RXEIE 0x2 /* Receive Event Interrupt Enable */ 583 #define EMAC_PTP_IE_RXGIE 0x4 /* Receive General Interrupt Enable */ 584 #define EMAC_PTP_IE_TXIE 0x8 /* Transmit Interrupt Enable */ 585 #define EMAC_PTP_IE_TXOVE 0x10 /* Transmit Overrun Error Interrupt Enable */ 586 #define EMAC_PTP_IE_RXOVE 0x20 /* Receive Overrun Error Interrupt Enable */ 587 #define EMAC_PTP_IE_ASIE 0x40 /* Auxiliary Snapshot Interrupt Enable */ 588 589 /* Bit masks for EMAC_PTP_ISTAT */ 590 591 #define EMAC_PTP_ISTAT_ALS 0x1 /* Alarm Status */ 592 #define EMAC_PTP_ISTAT_RXEL 0x2 /* Receive Event Interrupt Locked */ 593 #define EMAC_PTP_ISTAT_RXGL 0x4 /* Receive General Interrupt Locked */ 594 #define EMAC_PTP_ISTAT_TXTL 0x8 /* Transmit Snapshot Locked */ 595 #define EMAC_PTP_ISTAT_RXOV 0x10 /* Receive Snapshot Overrun Status */ 596 #define EMAC_PTP_ISTAT_TXOV 0x20 /* Transmit snapshot Overrun Status */ 597 #define EMAC_PTP_ISTAT_ASL 0x40 /* Auxiliary Snapshot Interrupt Status */ 598 599 600 /* Bit masks for RSI_PWR_CONTROL */ 601 #define PWR_ON 0x3 /* Power On */ 602 #define RSI_CMD_OD 0x40 /* Open Drain Output */ 603 /* legacy bit mask (below) provided for backwards code compatibility */ 604 #define SD_CMD_OD RSI_CMD_OD /* Open Drain Output */ 605 /* legacy bit mask (below) provided for backwards code compatibility */ 606 #define nSD_CMD_OD 0x0 607 /* legacy bit mask (below) provided for backwards code compatibility */ 608 #if 0 609 #define TBD 0x3c /* TBD */ 610 #endif 611 /* legacy bit mask (below) provided for backwards code compatibility */ 612 #define ROD_CTL 0x80 613 /* legacy bit mask (below) provided for backwards code compatibility */ 614 #define nROD_CTL 0x80 615 616 617 /* Bit masks for RSI_CLK_CONTROL */ 618 #define CLKDIV 0xff /* MC_CLK Divisor */ 619 #define CLK_EN 0x100 /* MC_CLK Bus Clock Enable */ 620 /* legacy bit mask (below) provided for backwards code compatibility */ 621 #define CLK_E CLK_EN /* MC_CLK Bus Clock Enable */ 622 /* legacy bit mask (below) provided for backwards code compatibility */ 623 #define nCLK_E 0x0 624 #define PWR_SV_EN 0x200 /* Power Save Enable */ 625 /* legacy bit mask (below) provided for backwards code compatibility */ 626 #define PWR_SV_E PWR_SV_EN /* Power Save Enable */ 627 /* legacy bit mask (below) provided for backwards code compatibility */ 628 #define nPWR_SV_E 0x0 629 #define CLKDIV_BYPASS 0x400 /* Bypass Divisor */ 630 /* legacy bit mask (below) provided for backwards code compatibility */ 631 #define nCLKDIV_BYPASS 0x0 632 #define BUS_MODE 0x1800 /* Bus width selection */ 633 /* legacy bit mask (below) provided for backwards code compatibility */ 634 #define WIDE_BUS 0x0800 /* Wide Bus Mode Enable */ 635 /* legacy bit mask (below) provided for backwards code compatibility */ 636 #define nWIDE_BUS 0x0 637 638 639 /* Bit masks for RSI_COMMAND */ 640 #define CMD_IDX 0x3f /* Command Index */ 641 #define CMD_RSP_EN 0x40 /* Response */ 642 /* legacy bit mask (below) provided for backwards code compatibility */ 643 #define CMD_RSP CMD_RSP_EN /* Response */ 644 /* legacy bit mask (below) provided for backwards code compatibility */ 645 #define nCMD_RSP 0x0 646 #define CMD_LRSP_EN 0x80 /* Long Response */ 647 /* legacy bit mask (below) provided for backwards code compatibility */ 648 #define CMD_L_RSP CMD_LRSP_EN /* Long Response */ 649 /* legacy bit mask (below) provided for backwards code compatibility */ 650 #define nCMD_L_RSP 0x0 651 #define CMD_INT_EN 0x100 /* Command Interrupt */ 652 /* legacy bit mask (below) provided for backwards code compatibility */ 653 #define CMD_INT_E CMD_INT_EN /* Command Interrupt */ 654 /* legacy bit mask (below) provided for backwards code compatibility */ 655 #define nCMD_INT_E 0x0 656 #define CMD_PEND_EN 0x200 /* Command Pending */ 657 /* legacy bit mask (below) provided for backwards code compatibility */ 658 #define CMD_PEND_E CMD_PEND_EN /* Command Pending */ 659 /* legacy bit mask (below) provided for backwards code compatibility */ 660 #define nCMD_PEND_E 0x0 661 #define CMD_EN 0x400 /* Command Enable */ 662 /* legacy bit mask (below) provided for backwards code compatibility */ 663 #define CMD_E CMD_EN /* Command Enable */ 664 /* legacy bit mask (below) provided for backwards code compatibility */ 665 #define nCMD_E 0x0 666 667 668 /* Bit masks for RSI_RESP_CMD */ 669 #define RESP_CMD 0x3f /* Response Command */ 670 671 /* Bit masks for RSI_DATA_LGTH */ 672 #define DATA_LENGTH 0xffff /* Data Length */ 673 674 675 /* Bit masks for RSI_DATA_CONTROL */ 676 #define DATA_EN 0x1 /* Data Transfer Enable */ 677 /* legacy bit mask (below) provided for backwards code compatibility */ 678 #define DTX_E DATA_EN /* Data Transfer Enable */ 679 /* legacy bit mask (below) provided for backwards code compatibility */ 680 #define nDTX_E 0x0 681 #define DATA_DIR 0x2 /* Data Transfer Direction */ 682 /* legacy bit mask (below) provided for backwards code compatibility */ 683 #define DTX_DIR DATA_DIR /* Data Transfer Direction */ 684 /* legacy bit mask (below) provided for backwards code compatibility */ 685 #define nDTX_DIR 0x0 686 #define DATA_MODE 0x4 /* Data Transfer Mode */ 687 /* legacy bit mask (below) provided for backwards code compatibility */ 688 #define DTX_MODE DATA_MODE /* Data Transfer Mode */ 689 /* legacy bit mask (below) provided for backwards code compatibility */ 690 #define nDTX_MODE 0x0 691 #define DATA_DMA_EN 0x8 /* Data Transfer DMA Enable */ 692 /* legacy bit mask (below) provided for backwards code compatibility */ 693 #define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */ 694 /* legacy bit mask (below) provided for backwards code compatibility */ 695 #define nDTX_DMA_E 0x0 696 #define DATA_BLK_LGTH 0xf0 /* Data Transfer Block Length */ 697 /* legacy bit mask (below) provided for backwards code compatibility */ 698 #define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */ 699 #define CEATA_EN 0x100 /* CE-ATA operation mode enable */ 700 #define CEATA_CCS_EN 0x200 /* CE-ATA CCS mode enable */ 701 702 /* Bit masks for RSI_DATA_CNT */ 703 #define DATA_COUNT 0xffff /* Data Count */ 704 705 /* Bit masks for RSI_STATUS */ 706 #define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ 707 /* legacy bit mask (below) provided for backwards code compatibility */ 708 #define nCMD_CRC_FAIL 0x0 709 #define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ 710 /* legacy bit mask (below) provided for backwards code compatibility */ 711 #define nDAT_CRC_FAIL 0x0 712 #define CMD_TIMEOUT 0x4 /* CMD Time Out */ 713 /* legacy bit mask (below) provided for backwards code compatibility */ 714 #define nCMD_TIMEOUT 0x0 715 #define DAT_TIMEOUT 0x8 /* Data Time Out */ 716 /* legacy bit mask (below) provided for backwards code compatibility */ 717 #define nDAT_TIMEOUT 0x0 718 #define TX_UNDERRUN 0x10 /* Transmit Underrun */ 719 /* legacy bit mask (below) provided for backwards code compatibility */ 720 #define nTX_UNDERRUN 0x0 721 #define RX_OVERRUN 0x20 /* Receive Overrun */ 722 /* legacy bit mask (below) provided for backwards code compatibility */ 723 #define nRX_OVERRUN 0x0 724 #define CMD_RESP_END 0x40 /* CMD Response End */ 725 /* legacy bit mask (below) provided for backwards code compatibility */ 726 #define nCMD_RESP_END 0x0 727 #define CMD_SENT 0x80 /* CMD Sent */ 728 /* legacy bit mask (below) provided for backwards code compatibility */ 729 #define nCMD_SENT 0x0 730 #define DAT_END 0x100 /* Data End */ 731 /* legacy bit mask (below) provided for backwards code compatibility */ 732 #define nDAT_END 0x0 733 #define START_BIT_ERR 0x200 /* Start Bit Error */ 734 /* legacy bit mask (below) provided for backwards code compatibility */ 735 #define nSTART_BIT_ERR 0x0 736 #define DAT_BLK_END 0x400 /* Data Block End */ 737 /* legacy bit mask (below) provided for backwards code compatibility */ 738 #define nDAT_BLK_END 0x0 739 #define CMD_ACT 0x800 /* CMD Active */ 740 /* legacy bit mask (below) provided for backwards code compatibility */ 741 #define nCMD_ACT 0x0 742 #define TX_ACT 0x1000 /* Transmit Active */ 743 /* legacy bit mask (below) provided for backwards code compatibility */ 744 #define nTX_ACT 0x0 745 #define RX_ACT 0x2000 /* Receive Active */ 746 /* legacy bit mask (below) provided for backwards code compatibility */ 747 #define nRX_ACT 0x0 748 #define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */ 749 /* legacy bit mask (below) provided for backwards code compatibility */ 750 #define nTX_FIFO_STAT 0x0 751 #define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */ 752 /* legacy bit mask (below) provided for backwards code compatibility */ 753 #define nRX_FIFO_STAT 0x0 754 #define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */ 755 /* legacy bit mask (below) provided for backwards code compatibility */ 756 #define nTX_FIFO_FULL 0x0 757 #define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */ 758 /* legacy bit mask (below) provided for backwards code compatibility */ 759 #define nRX_FIFO_FULL 0x0 760 #define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */ 761 /* legacy bit mask (below) provided for backwards code compatibility */ 762 #define nTX_FIFO_ZERO 0x0 763 #define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */ 764 /* legacy bit mask (below) provided for backwards code compatibility */ 765 #define nRX_DAT_ZERO 0x0 766 #define TX_DAT_RDY 0x100000 /* Transmit Data Available */ 767 /* legacy bit mask (below) provided for backwards code compatibility */ 768 #define nTX_DAT_RDY 0x0 769 #define RX_FIFO_RDY 0x200000 /* Receive Data Available */ 770 /* legacy bit mask (below) provided for backwards code compatibility */ 771 #define nRX_FIFO_RDY 0x0 772 773 /* Bit masks for RSI_STATCL */ 774 775 #define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */ 776 /* legacy bit mask (below) provided for backwards code compatibility */ 777 #define nCMD_CRC_FAIL_STAT 0x0 778 #define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */ 779 /* legacy bit mask (below) provided for backwards code compatibility */ 780 #define nDAT_CRC_FAIL_STAT 0x0 781 #define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */ 782 /* legacy bit mask (below) provided for backwards code compatibility */ 783 #define nCMD_TIMEOUT_STAT 0x0 784 #define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */ 785 /* legacy bit mask (below) provided for backwards code compatibility */ 786 #define nDAT_TIMEOUT_STAT 0x0 787 #define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */ 788 /* legacy bit mask (below) provided for backwards code compatibility */ 789 #define nTX_UNDERRUN_STAT 0x0 790 #define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */ 791 /* legacy bit mask (below) provided for backwards code compatibility */ 792 #define nRX_OVERRUN_STAT 0x0 793 #define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */ 794 /* legacy bit mask (below) provided for backwards code compatibility */ 795 #define nCMD_RESP_END_STAT 0x0 796 #define CMD_SENT_STAT 0x80 /* CMD Sent Status */ 797 /* legacy bit mask (below) provided for backwards code compatibility */ 798 #define nCMD_SENT_STAT 0x0 799 #define DAT_END_STAT 0x100 /* Data End Status */ 800 /* legacy bit mask (below) provided for backwards code compatibility */ 801 #define nDAT_END_STAT 0x0 802 #define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */ 803 /* legacy bit mask (below) provided for backwards code compatibility */ 804 #define nSTART_BIT_ERR_STAT 0x0 805 #define DAT_BLK_END_STAT 0x400 /* Data Block End Status */ 806 /* legacy bit mask (below) provided for backwards code compatibility */ 807 #define nDAT_BLK_END_STAT 0x0 808 809 /* Bit masks for RSI_MASKx */ 810 811 #define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */ 812 /* legacy bit mask (below) provided for backwards code compatibility */ 813 #define nCMD_CRC_FAIL_MASK 0x0 814 #define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */ 815 /* legacy bit mask (below) provided for backwards code compatibility */ 816 #define nDAT_CRC_FAIL_MASK 0x0 817 #define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */ 818 /* legacy bit mask (below) provided for backwards code compatibility */ 819 #define nCMD_TIMEOUT_MASK 0x0 820 #define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */ 821 /* legacy bit mask (below) provided for backwards code compatibility */ 822 #define nDAT_TIMEOUT_MASK 0x0 823 #define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */ 824 /* legacy bit mask (below) provided for backwards code compatibility */ 825 #define nTX_UNDERRUN_MASK 0x0 826 #define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */ 827 /* legacy bit mask (below) provided for backwards code compatibility */ 828 #define nRX_OVERRUN_MASK 0x0 829 #define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */ 830 /* legacy bit mask (below) provided for backwards code compatibility */ 831 #define nCMD_RESP_END_MASK 0x0 832 #define CMD_SENT_MASK 0x80 /* CMD Sent Mask */ 833 /* legacy bit mask (below) provided for backwards code compatibility */ 834 #define nCMD_SENT_MASK 0x0 835 #define DAT_END_MASK 0x100 /* Data End Mask */ 836 /* legacy bit mask (below) provided for backwards code compatibility */ 837 #define nDAT_END_MASK 0x0 838 #define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */ 839 /* legacy bit mask (below) provided for backwards code compatibility */ 840 #define nSTART_BIT_ERR_MASK 0x0 841 #define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */ 842 /* legacy bit mask (below) provided for backwards code compatibility */ 843 #define nDAT_BLK_END_MASK 0x0 844 #define CMD_ACT_MASK 0x800 /* CMD Active Mask */ 845 /* legacy bit mask (below) provided for backwards code compatibility */ 846 #define nCMD_ACT_MASK 0x0 847 #define TX_ACT_MASK 0x1000 /* Transmit Active Mask */ 848 /* legacy bit mask (below) provided for backwards code compatibility */ 849 #define nTX_ACT_MASK 0x0 850 #define RX_ACT_MASK 0x2000 /* Receive Active Mask */ 851 /* legacy bit mask (below) provided for backwards code compatibility */ 852 #define nRX_ACT_MASK 0x0 853 #define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */ 854 /* legacy bit mask (below) provided for backwards code compatibility */ 855 #define nTX_FIFO_STAT_MASK 0x0 856 #define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */ 857 /* legacy bit mask (below) provided for backwards code compatibility */ 858 #define nRX_FIFO_STAT_MASK 0x0 859 #define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */ 860 /* legacy bit mask (below) provided for backwards code compatibility */ 861 #define nTX_FIFO_FULL_MASK 0x0 862 #define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */ 863 /* legacy bit mask (below) provided for backwards code compatibility */ 864 #define nRX_FIFO_FULL_MASK 0x0 865 #define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */ 866 /* legacy bit mask (below) provided for backwards code compatibility */ 867 #define nTX_FIFO_ZERO_MASK 0x0 868 #define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */ 869 /* legacy bit mask (below) provided for backwards code compatibility */ 870 #define nRX_DAT_ZERO_MASK 0x0 871 #define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */ 872 /* legacy bit mask (below) provided for backwards code compatibility */ 873 #define nTX_DAT_RDY_MASK 0x0 874 #define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */ 875 /* legacy bit mask (below) provided for backwards code compatibility */ 876 #define nRX_FIFO_RDY_MASK 0x0 877 878 /* Bit masks for RSI_FIFO_CNT */ 879 #define FIFO_COUNT 0x7fff /* FIFO Count */ 880 881 /* Bit masks for RSI_CEATA_CONTROL */ 882 #define CEATA_TX_CCSD 0x1 /* Send CE-ATA CCSD sequence */ 883 884 /* Bit masks for RSI_ESTAT */ 885 #define SDIO_INT_DET 0x2 /* SDIO Int Detected */ 886 /* legacy bit mask (below) provided for backwards code compatibility */ 887 #define nSDIO_INT_DET 0x0 888 #define SD_CARD_DET 0x10 /* SD Card Detect */ 889 /* legacy bit mask (below) provided for backwards code compatibility */ 890 #define nSD_CARD_DET 0x0 891 #define CEATA_INT_DET 0x20 892 893 /* Bit masks for RSI_EMASK */ 894 #define SDIO_INT_DET_MASK 0x2 /* Mask SDIO Int Detected */ 895 /* legacy bit mask (below) provided for backwards code compatibility */ 896 #define SDIO_MSK SDIO_INT_DET_MASK /* Mask SDIO Int Detected */ 897 /* legacy bit mask (below) provided for backwards code compatibility */ 898 #define nSDIO_MSK 0x0 899 #define SD_CARD_DET_MASK 0x10 /* Mask Card Detect */ 900 /* legacy bit mask (below) provided for backwards code compatibility */ 901 #define SCD_MASK SD_CARD_DET_MASK /* Mask Card Detect */ 902 /* legacy bit mask (below) provided for backwards code compatibility */ 903 #define nSCD_MSK 0x0 904 #define CEATA_INT_DET_MASK 0x20 905 906 907 /* Bit masks for SDH_CFG */ 908 909 /* Left in for backwards compatibility */ 910 #define RSI_CLK_EN 0x1 911 /* legacy bit mask (below) provided for backwards code compatibility */ 912 #define CLKS_EN RSI_CLK_EN /* Clocks Enable */ 913 /* legacy bit mask (below) provided for backwards code compatibility */ 914 #define nCLKS_EN 0x0 915 #define SDIO4_EN 0x4 /* SDIO 4-Bit Enable */ 916 /* legacy bit mask (below) provided for backwards code compatibility */ 917 #define SD4E SDIO4_EN /* SDIO 4-Bit Enable */ 918 /* legacy bit mask (below) provided for backwards code compatibility */ 919 #define nSD4E 0x0 920 #define MW_EN 0x8 /* Moving Window Enable */ 921 /* legacy bit mask (below) provided for backwards code compatibility */ 922 #define MWE MW_EN /* Moving Window Enable */ 923 /* legacy bit mask (below) provided for backwards code compatibility */ 924 #define nMWE 0x0 925 #define RSI_RST 0x10 /* SDMMC Reset */ 926 /* legacy bit mask (below) provided for backwards code compatibility */ 927 #define SD_RST RSI_RST /* SDMMC Reset */ 928 /* legacy bit mask (below) provided for backwards code compatibility */ 929 #define nSD_RST 0x0 930 #define PU_DAT 0x20 /* Pull-up SD_DAT */ 931 /* legacy bit mask (below) provided for backwards code compatibility */ 932 #define PUP_SDDAT PU_DAT /* Pull-up SD_DAT */ 933 /* legacy bit mask (below) provided for backwards code compatibility */ 934 #define nPUP_SDDAT 0x0 935 #define PU_DAT3 0x40 /* Pull-up SD_DAT3 */ 936 /* legacy bit mask (below) provided for backwards code compatibility */ 937 #define PUP_SDDAT3 PU_DAT3 /* Pull-up SD_DAT3 */ 938 /* legacy bit mask (below) provided for backwards code compatibility */ 939 #define nPUP_SDDAT3 0x0 940 #define PD_DAT3 0x80 /* Pull-down SD_DAT3 */ 941 /* legacy bit mask (below) provided for backwards code compatibility */ 942 #define PD_SDDAT3 PD_DAT3 /* Pull-down SD_DAT3 */ 943 /* legacy bit mask (below) provided for backwards code compatibility */ 944 #define nPD_SDDAT3 0x0 945 946 947 /* Bit masks for RSI_RD_WAIT_EN */ 948 #define SDIO_RWR 0x1 /* Read Wait Request */ 949 /* legacy bit mask (below) provided for backwards code compatibility */ 950 #define RWR SDIO_RWR /* Read Wait Request */ 951 /* legacy bit mask (below) provided for backwards code compatibility */ 952 #define nRWR 0x0 953 954 /* Bit masks for RSI_PIDx */ 955 #define RSI_PID 0xff /* RSI Peripheral ID */ 956 957 958 #ifdef _MISRA_RULES 959 #pragma diag(pop) 960 #endif /* _MISRA_RULES */ 961 962 #endif /* _DEF_BF518_H */ 963